AM53CF94 Advanced Micro Devices, AM53CF94 Datasheet - Page 14

• Manufacturer Part Number: AM53CF94
• Description: Enhanced SCSI-2 Controller (ESC)
• Manufacturer: Advanced Micro Devices

DMAWR
DMA Write
(Input, Active Low)
This signal writes the data onto the DMA 15–0 and
DMAP 1–0 bus into the internal FIFO when DACK is
also active. When in the single bus mode this signal
must be tied to the WR signal.
RD
Read
(Input Active Low)
This signal reads the internal device registers and
places their contents on the data bus, when either CS
signal or DACK signal is active.
WR
Write
(Input Active Low)
This signal writes the internal device registers with the
value present on the (AD 7–0 bus or the DMA 15–0 and
DMAP 1–0 bus), when the CS signal is also active.
CS
Chip Select
(Input Active Low)
This signal enables the read and write of the device reg-
isters. CS enables access to any register (including the
FIFO) while the DACK enables access only to the FIFO.
CS and DACK should never be active simultaneously in
the single bus mode, they may however be active simul-
taneously in the dual bus mode provided the CS signal is
not enabling access to the FIFO.
INT
Interrupt
(Output, Active Low, Open Drain)
This signal is a non-maskable interrupt flag to the host
processor. This signal is latched on the output on the
high going edge of the clock. This flag may be cleared by
reading the Interrupt Status Register (ISTAT) or by per-
forming a device reset (hard or soft). This flag is not
cleared by a SCSI reset.
DFMODE
Differential Mode
(Input, Active Low)
This input is available only on the Am53CF96. This input
configures the SCSI bus to either single ended or differ-
ential mode. When this input is active, the device oper-
ates in the differential SCSI mode. The SCSI data is
available on the SD 7–0 lines and the high active trans-
ceiver enables on the SDC 7–0 outputs. When this input
is inactive, the device operates in the single ended SCSI
mode. The SCSI input data is available on SD 7–0 lines
and the output data is available on SDC 7–0 lines. In the
single ended SCSI mode, the SD 7–0 and the SDC 7–0
buses can be tied together externally.
14
AMD
Am53CF94/Am53CF96
P R E L I M I N A R Y
BUSMD 1–0
Bus Mode
(Input, Active High)
These inputs configure the device for single bus or dual
bus operation and the DMA bus width.
CLK
Clock
(Input)
Clock input used to generate all the internal device tim-
ings. The maximum frequency of this input is 40 MHz.
and a minimum of 10 MHz to maintain the SCSI bus
timings.
RESET
Reset
(Input, Active High)
This input when active resets the device. The RESET in-
put must be active for at least two CLK periods after the
voltage on the power inputs have reached Vcc
minimum.
SCSI Interface Signals
SD 7–0
SCSI Data
(Input/Output, Active Low, Schmitt Trigger)
When the device is configured in the Single Ended SCSI
Mode (DFMODE inactive) these pins are defined as in-
puts for the SCSI data bus. When the device is config-
ured in the Differential SCSI Mode (DFMODE active)
these pins are defined as bidirectional SCSI data bus.
BUSMD1
1
1
0
0
BUSMD0 Bus Configuration
1
0
1
0
Two buses: 8-bit Host Bus
and 16-bit DMA Bus
Register Address on A 3–0
and Data on AD Bus
Two buses: Multiplexed
and byte control
Register Address on AD 3–0
and Data on AD Bus
Single bus: 8-bit Host Bus
and 16-bit DMA Bus
Register Address on A 3–0
and Data on DMA Bus
Single bus: 8-bit Host Bus
and 8-bit DMA Bus
Register Address on A 3–0
and Data on DMA Bus