SAA5500PS Philips Semiconductors, SAA5500PS Datasheet - Page 51

• Manufacturer Part Number: SAA5500PS
• Description: Standard TV Microcontrollers with On-Screen Display(OSD)
• Manufacturer: Philips Semiconductors

Philips Semiconductors
18.1.6.7
One of the uses of packet 26 is to transmit characters
which are not in the basic teletext character set. The family
automatically decodes packet 26 data and, if a character
corresponding to that being transmitted is available in the
character set, automatically writes the appropriate
character code into the correct location in the teletext
memory. This is not a full implementation of the packet 26
specification allowed for in level 2 teletext, and so is often
referred to as level 1.5.
By convention, the packets 26 for a page are transmitted
before the normal packets. To prevent the default
character data overwriting the packet 26 data the device
incorporates a mechanism which prevents packet 26 data
from being overwritten. The mechanism is disabled when
the Spanish national option is detected as the Spanish
transmission system sends even parity (i.e. incorrect)
characters in the basic page locations corresponding to
the characters sent via packet 26 and these will not
overwrite the packet 26 characters anyway. The special
treatment of Spanish national option is prevented if
TXT12.ROM VER3 is logic 0 or if the TXT8.DISABLE
SPANISH is set.
Packet 26 data is processed regardless of the
TXT1.EXT PKT OFF bit, but setting theTXT1.X26 OFF
disables packet 26 processing.
The TXT8.PKT26 RECEIVED bit is set by the hardware
whenever a character is written into the page memory by
the packet 26 decoding hardware. The flag can be reset by
writing a logic 0 into the SFR bit.
18.1.7
The family is capable of acquiring Level 1.5 625-line and
525-line World System Teletext.
18.2
When a packet 8/30 is detected, or a packet 4/30 when the
device is receiving a 525 line transmission, the
TXT13. PKT 8/30 flag is set. The flag can be reset by
writing a 0 into the SFR bit.
1999 Oct 27
handbook, full pagewidth
Standard TV microcontrollers with
On-Screen Display (OSD)
Broadcast service data detection
WST A
Packet 26 processing
CQUISITION
row 25
column
0
teletext page
header data
9
10
byte 11
VPS
Fig.21 VPS data storage.
11
12
byte 12
VPS
13 14
51
byte 13
18.3
When the TXT0.VPS ON bit is set, any VPS data present
on line 16, field 0 of the CVBS signal at the input of the
teletext decoder is error checked and stored in row 25,
block 9 of the basic page memory. The device
automatically detects whether teletext or VPS is being
transmitted on this line and decodes the data
appropriately.
Each VPS byte in the memory consists of 4 biphase
decoded data bits (bits 0 to 3), a biphase error flag (bit 4)
and three logic 0s (bits 5 to 7).
The TXT13.VPS RECEIVED bit is set by the hardware
whenever VPS data is acquired.
Full details of the VPS system can be found in the
“Specification of the Domestic Video Programme Delivery
Control System (PDC); EBU Tech. 3262-E”.
18.4
The Wide Screen Signalling data transmitted on line 23
gives information on the aspect ratio and display position
of the transmitted picture, the position of subtitles and on
the camera/film mode. Some additional bits are reserved
for future use. A total of 14 data bits are transmitted.
All of the available data bits transmitted by the Wide
Screen Signalling signal are captured and stored in SFRs
WSS1, WSS2 and WSS3. The bits are stored as groups of
related bits, and an error flag is provided for each group to
indicate when a transmission error has been detected in
one or more of the bits in the group.
Wide screen signalling data is only acquired when the
TXT8.WSS ON bit is set.
The TXT8.WSS RECEIVED bit is set by the hardware
whenever wide screen signalling data is acquired. The flag
can be reset by writing a logic 0 into the SFR bit.
VPS
15 16
VPS acquisition
WSS acquisition
byte 14
VPS
17 18
byte 15
VPS
19 20
byte 4
VPS
21 22
byte 5
VPS
MBK964
Preliminary specification
23
SAA55xx