SAA5500PS Philips Semiconductors, SAA5500PS Datasheet - Page 33

• Manufacturer Part Number: SAA5500PS
• Description: Standard TV Microcontrollers with On-Screen Display(OSD)
• Manufacturer: Philips Semiconductors

Philips Semiconductors
12 INTERRUPT SYSTEM
The device has six interrupt sources, each of which can be
enabled or disabled. When enabled each interrupt can be
assigned one of two priority levels. There are four
interrupts that are common to the 80C51, two of these are
external interrupts (EX0 and EX1) and the other two are
timer interrupts (ET0 and ET1). In addition to the
conventional 80C51 interrupts, one application specific
interrupt is incorporated internal to the device which has
following functionality:
12.1
Each of the individual interrupts can be enabled or
disabled by setting or clearing the relevant bit in the
Interrupt Enable Register (IE). All interrupt sources can
also be globally disabled by clearing the EA bit (IE.7).
12.2
Each interrupt source can be assigned one of two priority
levels. The interrupt priorities are defined by the Interrupt
Priority Register (IP). A low priority interrupt can be
interrupted by a high priority interrupt, but not by another
low priority interrupt. A high priority interrupt can not be
interrupted by any other interrupt source. If two requests of
different priority levels are received simultaneously, the
request with the highest priority level is serviced.
1999 Oct 27
Display Busy interrupt (EBUSY). An interrupt is
generated when the display enters either a Horizontal or
Vertical Blanking Period. i.e. Indicates when the
microcontroller can update the Display RAM without
causing undesired effects on the screen. This interrupt
can be configured in one of two modes using the
Memory Mapped Register (MMR) Configuration
(address 87FFH, bit TXT/V):
– Text Display Busy. An interrupt is generated on each
– Vertical Display Busy. An interrupt is generated on
Standard TV microcontrollers with
On-Screen Display (OSD)
active horizontal display line when the Horizontal
Blanking Period is entered
each vertical display field when the Vertical Blanking
Period is entered.
Interrupt enable structure
Interrupt enable priority
33
If requests of the same priority level are received
simultaneously, an internal polling sequence determines
which request is serviced. Thus, within each priority level
there is a second priority structure determined by the
polling sequence as defined in Table 8.
Table 8 Interrupt priority (within same level)
12.3
The processor acknowledges an interrupt request by
executing a hardware generated LCALL to the appropriate
servicing routine. The interrupt vector addresses for each
source are shown in Table 8.
12.4
The external interrupt can be programmed to be either
level-activated or transition-activated by setting or clearing
the IT0/IT1 bits in the Timer Control SFR (TCON).
Table 9 External interrupt activation
The external interrupt INT1 differs from the standard
80C51 interrupt in that it is activated on both edges when
in edge sensitive mode. This is to allow software pulse
width measurement for handling remote control inputs.
ITx
0
1
SOURCE
EBUSY
active LOW
Interrupt vector address
Level/edge interrupt
EX0
EX1
ES2
ET0
ET1
LEVEL
INT0 = negative edge
INTI = positive and negative edge
WITHIN LEVEL
PRIORITY
highest
lowest
Preliminary specification
EDGE
SAA55xx
INTERRUPT
VECTOR
000BH
001BH
002BH
0003H
0013H
0033H