AM79C90 Advanced Micro Devices, AM79C90 Datasheet - Page 56

• Manufacturer Part Number: AM79C90
• Description: CMOS Local Area Network Controller for Ethernet (C-LANCE)
• Manufacturer: Advanced Micro Devices

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Process/Power
Consumption
FIFOs
Transmit Lockout Due to
Receive
Per-Packet FCS
Backoff Algorithm
TX Descriptor Zero Buffer
Byte Count Capability
Interframe Spacing (IFS)
Behavior
“Heartbeat OK” (No CERR)
Definition
Burn-In Option
RX Descriptor Zero Buffer
Byte Count Handling
Receive Lockup
ALE Behavior
External Loopback on a Live
Network
Software Reset (STOP Bit)
Handling
CSR0 Slave Read Data
Stability
INEA Bit Behavior
Effect of Setting the STOP
Bit on CSR0 Bits
AC Specification Changes
Description
Table B-1. Comparison Summary of the C-LANCE and LANCE Devices
0.8-micron CS-21S CMOS process
I
Dual FIFOs: 48-byte TX, 64-byte RX
Will not occur with dual FIFOs and
enhanced microcode.
packet addition of CRC when DTCR is set in
the MODE register.
standard backoff algorithm.
Allows TX buffer byte count of zero.
a) Implements two-part deferral after
b) Part 1 of two-part deferral after receive is
c) Heartbeat window = 4 s
d) Receive blind time after receive less than
Heartbeat OK if collision is asserted at any
time from the beginning of the transmission
to the end of the heartbeat window.
#08 (t
#18 (t
#30 (t
#45 (t
longer available.
Unpredictable results when the RX
Descriptor Buffer Byte Count is set to zero.
Transmit descriptor bit is used to allow per-
Selectable Modified Backoff Algorithm or
Will not occur.
ALE may be driven HIGH at end of bus
mastership when ACON is set to 0. When
ACON is set to 1, ALE is not driven LOW at
end of bus mastership period.
No problems.
a) STOP bit in CSR0 is latched. When STOP
b) CSR1 and CSR2 contents are preserved
CSR0 latched during Slave reads to
guarantee timing on DAL lines.
INEA bit can be set in CSR0 at any time,
regardless of the state of the STOP bit.
Setting the STOP bit in CSR0 when the
STOP bit is already set does not affect any
of the other bits in CSR0 (they are not
cleared).
#06 (t
The burn-in option for the C-LANCE is no
CC
transmit
6 s
500 ns
is set, the slave cycle is allowed to
complete before the C-LANCE resets.
when the STOP bit is set to one.
50 mA
TEP
TDP
RDS
RDAS
RDYS
) maximum = 60 ns
) maximum = 60 ns
) minimum = 35 ns
) minimum = 65 ns
) minimum = 40 ns
Am79C90 C-LANCE
Am79C90
NS-8B NMOS process
I
May occur in high receive rate situations
with “less than optimal” bus latencies.
No per-packet CRC control provided.
Only standard backoff algorithm available.
a) One-part deferral after transmit
b) Part 1 of two-part deferral after receive is
c) Heartbeat window = 2 s
d) Receive blind time after receive = 4.1 s
Heartbeat OK if collision is asserted during
the heartbeat window.
ALE may be driven LOW at end of bus
mastership when ACON is set to 1. When
ACON is set to 0, ALE is not driven HIGH at
end of bus mastership period.
May receive invalid loopback failure
indications.
a) STOP bit in CSR0 not latched and will
b) CSR1 and CSR2 are not preserved when
CSR0 not latched during Slave read cycles
(could give timing violations on DAL lines).
INEA cannot be set in CSR0 while the STOP
bit is set.
Setting the STOP bit in CSR0 causes all of
the other bits in CSR0 to clear, regardless of
the previous state of the STOP bit.
#06 (t
#08 (t
#18 (t
#30 (t
#45 (t
Interprets a BCNT field setting of zero in a
receive descriptor as a 4096-byte buffer.
Single FIFO: 48-byte TX/RX
No capability for TX buffer byte count of zero.
May occur when bus latency is large.
CC
4.1 s
reset the device immediately when
written.
the STOP bit is set to one.
270 mA
TEP
TDP
RDS
RDAS
RDYS
) maximum = 70 ns
) maximum = 70 ns
) minimum = 40 ns
) minimum = 50 ns
) minimum = 75 ns
Am7990 LANCE