AM79C90 Advanced Micro Devices, AM79C90 Datasheet - Page 12

• Manufacturer Part Number: AM79C90
• Description: CMOS Local Area Network Controller for Ethernet (C-LANCE)
• Manufacturer: Advanced Micro Devices

Buffer Management
A key feature of the C-LANCE and its on-board DMA
channel is the flexibility and speed of communication
between the C-LANCE and the host microprocessor
through common memory locations. The basic organi-
zation of the buffer management is a circular queue of
tasks in memory called descriptor rings as shown in
Figures 2-1 and 2-2. There are separate descriptor rings
to describe transmit and receive operations. Up to 128
tasks may be queued up on a descriptor ring awaiting
execution by the C-LANCE. Each entry in a descriptor
ring holds a pointer to a data memory buffer and an entry
for the length of the data buffer. Data buffers can be
chained or cascaded to handle a long packet in multiple
data buffer areas. The C-LANCE searches the descrip-
tor rings in a “lookahead” manner to determine the next
empty buffer in order to chain buffers together or to han-
dle back-to-back packets. As each buffer is filled,
12
AMD
Initialization
Block
C-LANCE CSR Registers
Pointer to Initialization Block
Mode of Operation
Physical Address
Logical Address Filter
Pointer to Receive Ring
Number of Receive Entries (N)
Pointer to Transmit Ring
Number of Transmit Entries (M)
Figure 2-2. C-LANCE Memory Management
P R E L I M I N A R Y
Am79C90
Receive Descriptor Ring
Transmit Descriptor Ring
Address of Receive Buffer 1
Buffer 1 Status
Buffer 1 Byte Count
Buffer 1 Message Count
Address of Transmit Buffer 1
Buffer 1 Status
Buffer 1 Byte Count
Buffer 1 Error Status
the “own” bit is reset, allowing the host processor to
process the data in the buffer.
C-LANCE Interface
CSR bits such as ACON, BCON and BSWP are used for
programming the pin functions used for different inter-
facing schemes. For example, ACON is used to pro-
gram the polarity of the Address Strobe signal
(ALE/AS).
BCON is used for programming the pins, for handling
either the BYTE/WORD method for addressing word or-
ganized, byte addressable memories where the BYTE
signal is decoded along with the least significant ad-
dress bit to determine upper or lower byte, or an explicit
scheme in which two signals labeled as BYTE MASK
(BM0 and BM1) indicate which byte is addressed. When
M
M
M
M
N
N
N
N
2
2
2
2
2
2
2
2
Transmit Buffer
Receive Buffer
Packet
Packet
Packet
Packet
Packet
Packet
Data
Data
Data
Data
Data
Data
M
N
1
2
1
2
17881B-8