AM79213 Legerity, AM79213 Datasheet - Page 33

• Manufacturer Part Number: AM79213
• Description: (AM79C203/031 / AM79213) PCM CODEC
• Manufacturer: Legerity

Master Clock
For 2.048 MHz ± 100 ppm, 4.096 MHz ± 100 ppm, or 8.192 MHz ± 100 ppm operation:
Notes:
1. DCLK may be stopped in the High or Low state indefinitely without loss of information.
2. The PCM clock (PCLK) frequency must be an integer multiple of the frame sync (FS) frequency with an accuracy of 800 ppm
3. TSC is delayed from FS by a typical value of N • tPCY, where N is the value stored in the time/clock slot register.
4. t
5. There is special circuitry that will prevent high-power dissipation from occurring when the DXA or DXB pins of two ASLAC
6. The first data bit is enabled on the falling edge of Chip Select or on the falling edge of DCLK, whichever occurs last. If chip
7. The ASLAC device requires 40 cycles of the 8 MHz internal clock (5 µs) between SIO operations. If the MPI is being accessed
No.
relative to the MCLK frequency. This allowance includes any jitter that may occur between the PCM signals (FS, PCLK) and
MCLK. The actual PCLK rate is dependent on the number of channels allocated within a frame. The ASLAC device supports
2 to128 channels. The minimum clock frequency is 128 kHz. A PCLK of 1.544 MHz may be used for standard U.S. transmission
systems.
The maximum load capacitance on TSC is 150 pF and the minimum pullup resistance is 360 Ω.
devices are tied together and one ASLAC device starts to transmit before the other has gone into a high-impedance state.
select is held Low for less than eight clocks, no command or data is accepted. If chip select is held Low for more than eight
clocks, the last 8 data bits are used as command or data.
while the MCLK (or PCLK if in combined clock mode) input is not active, a Chip Select Off time of 20 µs is required.
37
38
39
40
41
TSO
is defined as the time at which the output driver turns off. The actual delay time is dependent on the load circuitry.
Symbol
t
t
t
t
t
MCY
MCR
MCH
MCF
MCL
Master clock period (2.048 MHz)
Master clock period (4.096 MHz)
Master clock period (8.192 MHz)
Rise time of clock
Fall time of clock
MCLK High pulse width
MCLK Low pulse width
Parameter
ASLIC/ASLAC Products
Table 9. Master Clock
488.23
244.11
122.05
Min.
48
48
488.28
244.14
122.07
Typ.
488.33
244.17
122.09
Max.
15
15
Units
ns
ns
ns
ns
ns
ns
ns
Note
2
33