ISPLSI5512VA-100LB388 Lattice Semiconductor, ISPLSI5512VA-100LB388 Datasheet - Page 3

• Manufacturer Part Number: ISPLSI5512VA-100LB388
• Description: In-System Programmable 3.3V SuperWIDE High Density PLD
• Manufacturer: Lattice Semiconductor

The 160 product terms are grouped in 32 sets of five and
sent into a Product Term Sharing Array (PTSA) which
allows sharing up to a maximum of 35 product terms for
a single function. Alternatively, the PTSA can be by-
passed for functions of five product terms or less. The
five extra product terms are used for shared GLB con-
trols, set, reset, clock, clock enable and output enable.
The 32 registered macrocells in the GLB are driven by the
32 outputs from the PTSA or the PTSA bypass. Each
macrocell contains a programmable XOR gate, a pro-
grammable register/latch/toggle flip-flop and the
necessary clocks and control logic to allow combinatorial
or registered operation. The macrocells each have two
outputs, which can be fed back through the Global
Routing Pool. This dual output capability from the
macrocell allows efficient use of the hardware resources.
One output can be a registered function for example,
while the other output can be an unrelated combinatorial
function. A direct register input from the I/O pad facilitates
efficient use of this feature to construct high-speed input
registers.
Macrocell registers can be clocked from one of several
global or product term clocks available on the device. A
global and product term clock enable is also provided,
eliminating the need to gate the clock to the macrocell
registers. Reset and preset for the macrocell register is
provided from both global and product term signals. The
macrocell register can be programmed to operate as a D-
type register, a D-type latch or a T-type flip flop.
The 32 outputs from the GLB can drive both the Global
Routing Pool and the device I/O cells. The Global Routing
Pool contains one line from each macrocell output and
one line from each I/O pin.
The input buffer threshold has programmable TTL/3.3V/
2.5V compatible levels. The output driver can source
Table 1. ispLSI 5000VA Family
ispLSI 5000V Description (Continued)
D
s i
s i
s i
e
p
p
p
v
L
L
L
c i
I S
I S
I S
e
5
5
5
2
3
5
5
8
1
6
4
2
V
V
V
A
A
A
G
L
1
1
8
B
2
6
s
M
a
c
3
2
5
o r
5
8
1
6
4
2
c
l e
s l
2
0
1
1
8
4
4
p f
—
3
4
4
4mA and sink 8mA in 3.3V mode. The output drivers have
a separate VCCIO reference input which is independent
of the main VCC supply for the device. This feature allows
the output drivers to drive either 3.3V or 2.5V output
levels while the device logic and the output current drive
is always powered from 3.3V. The output drivers also
provide individually programmable edge rates and open
drain capability. A programmable pullup resistor is pro-
vided to tie off unused inputs and a programmable
bus-hold latch is available to hold tristate outputs in their
last valid state until the bus is driven again by some
device.
The ispLSI 5000V Family features 3.3V, non-volatile in-
system programmability for both the logic and the
interconnect structures, providing the means to develop
truly reconfigurable systems. Programming is achieved
through the industry standard IEEE 1149.1-compliant
Boundary Scan interface. Boundary Scan test is also
supported through the same interface.
An enhanced, multiple cell security scheme is provided
that prevents reading of the JEDEC programming file
when secured. After the device has been secured using
this mechanism, the only way to clear the security is to
execute a bulk-erase instruction.
The ispLSI 5000V Family ranges from 256 macrocells to
512 macrocells and operates from a 3.3V power supply.
All family members will be available with multiple pack-
age options. The ispLSI 5000V Family device matrix
showing the various bondout options is shown in the table
below.
The interconnect structure (GRP) is very similar to Lattice's
existing ispLSI 1000, 2000 and 3000 families, but with an
enhanced interconnect structure for optimal pin locking
and logic routing. This eliminates the need for registered
I/O cells or an Output Routing Pool.
B
/ I
/ I
ispLSI 5000V Family Members
Specifications ispLSI 5512VA
O
O
G
A
2
0
1
1
1
8
4
4
4
4
4
4
P
P
a
Q
/ I
/ I
/ I
c
O
O
O
F
k
P
a
g
e
T
2
y
1
1
1
7
p
9
9
9
2
2
2
2
e
B
/ I
/ I
/ I
G
O
O
O
A
3
2
2
8
8
8
8
—
8
8
B
/ I
/ I
G
O
O
A