ISPLSI5512VA-100LB388 Lattice Semiconductor, ISPLSI5512VA-100LB388 Datasheet - Page 15

• Manufacturer Part Number: ISPLSI5512VA-100LB388
• Description: In-System Programmable 3.3V SuperWIDE High Density PLD
• Manufacturer: Lattice Semiconductor

1. Internal Timing Parameters are not tested and are for reference only.
Refer to Timing Model in this data sheet for further details.
INPUT
I/O
Pad
Internal Timing Parameters
Input
PARAM
GRP
t
t
Global Control Delays
t
t
t
t
t
t
t
ispLSI 5512VA Timing Model
Pad
grpi
grpm
gclk01
gclk23
gclken0
gclken1
grst
goe
toe
Input
Buffer
t
t
idcom
#21
#20
idreg
Input Buffers
#57
#58
#59
#60
#61
#62
#63
Dedicated
57
58
59
60
61
62
63
64
65
#
2
t
t
t
t
t
t
t
gclk0
gclk123
gclken0
gclken1
grst
goe
toe
#56
GRP Delay from I/O Pad
GRP Delay from Macrocell
Global Clock 0 or 1 Delay
Global Clock 2 or 3 Delay
Global CLKEN 0 Delay
Global CLKEN 1 Delay
Global Set/Reset Delay
Global OE Delay
Test OE Delay
#55
GRP
t
t
grpm
grpi
Over Recommended Operating Conditions
DESCRIPTION
1
AND Array
t
t
#39
andhs
andlp
#38
#40
#44
#42
t
t
t
5ptcom
ptsacom
5ptxcom
PT Controls
#49
#46
#50
#47
#48
#51
#52
#53
#54
GLB/Macrocell
PTSA
15
t
t
t
tpcken
tscken
t
t
t
t
sck
pck
ptsacken
srst
prst
poe
gpoe
#41
#45
#43
Specifications ispLSI 5512VA
t
t
t
5ptxreg
ptsareg
5ptreg
MIN
–
–
–
–
–
–
–
–
–
-110
#37
#29
#30
#32
#33
#31
#35
#34
#36
Register
MAX MIN
14.2
t
t
t
t
t
t
t
t
1.5
1.2
1.2
2.2
1.7
2.7
4.8
4.7
ftog
mbp
mlat
msu
mh
mco
mhce
msuce
t
mrst
–
–
–
–
–
–
–
–
–
-100
MAX MIN
15.8
Buffer Delays
#22
#23
#24
1.2
1.7
2.7
2.4
3.4
6.3
6.2
2
t
t
t
Output
odcom
odreg
odz
Buffer
–
–
–
–
–
–
–
–
–
-70
#28
#27
#25
#26
MAX
23.4
1.2
2.4
4.4
3.4
5.4
9.4
9.4
Slew
3
t
t
t
t
Timing Rev 4.0
slsd
slfd
slf
sls
UNIT
OUTPUT
Pad
ns
ns
ns
ns
ns
ns
ns
ns
ns
I/O