ISPLSI3256E-100LB320 Lattice Semiconductor, ISPLSI3256E-100LB320 Datasheet

ISPLSI3256E-100LB320

Manufacturer Part Number

ISPLSI3256E-100LB320

Description

In-System Programmable High Density PLD

Manufacturer

Lattice Semiconductor

Datasheet

1.ISPLSI3256E-100LB320.pdf (15 pages)

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• HIGH-DENSITY PROGRAMMABLE LOGIC

• HIGH PERFORMANCE E

• IN-SYSTEM PROGRAMMABLE

• 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE

• OFFERS THE EASE OF USE AND FAST SYSTEM

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

3256e_08

Features

— 256 I/O Pins

— 12000 PLD Gates

— 512 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

— Small Logic Block Size for Random Logic

—

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

— 5V In-System Programmable (ISP™) using Lattice

— Increased Manufacturing Yields, Reduced Time-to-

— Reprogram Soldered Devices for Faster Debugging

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

— Five Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to Mini-

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

— PC and UNIX Platforms

Market, and Improved Product Quality

ISP or Boundary Scan Test (IEEE 1149.1) Protocol

Machines, Address Decoders, etc.

Logic and Structured Designs

mize Switching Noise

Interconnectivity

Tools, Timing Simulator and ispANALYZER™

max = 100 MHz Maximum Operating Frequency

pd = 10 ns Propagation Delay

CMOS

TECHNOLOGY

In-System Programmable High Density PLD

The ispLSI 3256E is a High Density Programmable Logic

Device containing 512 Registers, 256 Universal I/O pins,

five Dedicated Clock Input Pins, 16 Output Routing Pools

(ORP) and a Global Routing Pool (GRP) which allows

complete inter-connectivity between all of these ele-

ments.

programmability and in-system diagnostic capabilities.

The ispLSI 3256E offers non-volatile reprogrammability

of the logic, as well as the interconnect to provide truly

reconfigurable systems.

The basic unit of logic on the ispLSI 3256E device is the

Twin Generic Logic Block (Twin GLB) labelled A0, A1...H3.

There are a total of 32 Twin GLBs in the ispLSI 3256E

device. Each Twin GLB has 24 inputs, a programmable

AND array and two OR/Exclusive-OR Arrays and eight

outputs which can be configured to be either combinato-

rial or registered. All Twin GLB inputs come from the

GRP.

Functional Block Diagram

Description

The ispLSI 3256E features 5V in-system

ORP

ispLSI

Global Routing Pool

Array

D Q

ORP

Twin

GLB

3256E

ORP

June 2002

Boundary

0139A/3256E

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