ML4821IP Micro Linear, ML4821IP Datasheet
ML4821IP
Related parts for ML4821IP
ML4821IP Summary of contents
Page 1
... Large oscillator amplitude for better noise immunity Output driver internally limited to 17V “Sleep mode” shutdown input * Some Packages Are Obsolete + V REF – + 0.7V – – OSC V REF Micro Linear ML4821* SLEEP V REF UNDER VOLTAGE GND LOCKOUT LIMIT 17V OUT PGND R T SYNC ...
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... PGND OVP 11 SOFT START SYNC 10 PIN NAME 10 (12) SYNC 11 (13) OVP 12 (14 (15) PWR 14 (16) OUT 15 (17 (18 (19 (20) GND Micro Linear ML4821 20-Pin SOIC (S20) I GND 1 20 LIM IA– REF IA OUT ...
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... CC 1mA < I < 20mA O line, load, temp 10Hz to 10kHz T = 125 C, 1000 hrs REF 2 < EA OUT < 6V 12V < V < 24V CC EA OUT = 4V, INV = 5.5V EA OUT = 4.0V, INV = 4.8V Micro Linear ML4821 ) JA = 15V (Notes 1 & 2). CC MIN TYP. MAX UNITS 90 100 110 kHz ...
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... V = 1.75V INV RMS V = 4.8V 2.6V INV RMS V = 4.8V 5.2V INV RMS V = 5.2V 5.2V INV RMS V = 4.8V 500 A, INV SINE V = 1.75V RMS Output Off Output On Micro Linear MIN TYP MAX UNITS 7.0 7 0.5 V 1.0 MHz –22 –38 –50 A – –0.15 –1 A 400 nA 80 100 dB 65 ...
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... Gain Modulator gain is defined as: I INEA OUT (Continued) CONDITIONS I = 20mA OUT I = 200mA OUT I = –20mA OUT I = –200mA OUT I = –5mA OUT 1000pF L Start-up 14V Operating 35mA CC Micro Linear ML4821 MIN TYP. MAX UNITS 0.1 0.4 V 1 13.4 V 0.1 0 14.5 16.5 V 8.5 11.0 V 4.4 V 0.6 1 ...
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... REF 1000 – 100 Figure 2. Oscillator Timing Resistance vs. Frequency. Micro Linear . SENSE pin, and in an inverse-square SINE pin. At very low voltages RMS pin, the gain modulator enforces a power input via a dropping SINE 150pF 330pF 1nF 680pF 10 20 ...
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... This is a very useful feature since in many cases the load for a PFC is a constant power load. The input current has to go high to compensate for a drop in the input voltage. Micro Linear ML4821 V = 15V ...
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... UVLO state when the OVP pin is pulled below CC 0.7V. 5.5 4.5 3.5 2.5 1.5 1.0 400 500 Figure 8. Under-Voltage Lockout Block Diagram. 0 –4.0 –8.0 –12 – 25°C A –20 – Figure 10. Reference Load Regulation. Micro Linear – 4.4V + LOGIC ENABLE POWER V REF V REF INTERNAL CC – 15 BIAS + –55° 125° ...
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... L1. The configuration shown delivers a voltage proportional to the PFC output bus voltage. R10 39k OUT N 14V S Figure 11. Bias and Start-up Circuit. power to the PIN 15 1000 F Micro Linear ML4821 9 ...
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... EA– RMS OVP 9 10 SOFT START SYNC C6 R14 43nF 91k R21 6.2k C7 R15 0.47 F 27k Figure 12. 200W Output PFC Circuit Micro Linear + D10 MUR850 C14 DC OUT 470 F 382V C19 270 F – 450V R20 825k R19 R18 10.2k 825k C11 R17 750pF 10.5k ...
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... BSC (1.27 - 1.65) (2.54 BSC) 0.015 MIN (0.38 MIN) SEATING PLANE 0.016 - 0.022 (0.40 - 0.56) Package: S20 20-Pin SOIC 0.291 - 0.301 0.398 - 0.412 (7.39 - 7.65) (10.11 - 10.47) 0.095 - 0.107 (2.41 - 2.72) 0.005 - 0.013 SEATING PLANE (0.13 - 0.33) Micro Linear ML4821 0.295 - 0.325 (7.49 - 8.26) 0.008 - 0.012 0º - 15º (0.20 - 0.31) 0º - 8º 0.022 - 0.042 0.007 - 0.015 (0.56 - 1.07) (0.18 - 0.38) 11 ...
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... ML4821 ORDERING INFORMATION PART NUMBER ML4821CP ML4821CS ML4821IP ML4821IS © Micro Linear 1997 Micro Linear is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; ...