ML4804 Fairchild, ML4804 Datasheet - Page 12

• Manufacturer Part Number: ML4804
• Description: Power Factor Correction and PWM Controller Combo
• Manufacturer: Fairchild

ML4804
Generating V
The ML4804 is a voltage-fed part. It requires an external
15V, ±10% (or better) shunt voltage regulator, or some
other V
the part at 15V nominal. This allows low power dissipation
while at the same time delivering 13V nominal gate drive
at the PWM OUT and PFC OUT outputs. If using a Zener
diode for this function, it is important to limit the current
through the Zener to avoid overheating or destroying it.
This can be easily done with a single resistor in series
with the Vcc pin, returned to a bias supply of typically
18V to 20V. The resistor’s value must be chosen to meet
the operating current requirement of the ML4804 itself
(8.5mA, max.) plus the current required by the two gate
driver outputs.
EXAMPLE:
With a V
driving a total gate charge of 90nC at 100kHz (e.g., 1
IRF840 MOSFET and 2 IRF820 MOSFETs), the gate driver
current required is:
Choose R
The ML4804 should be locally bypassed with a 1.0µF
ceramic capacitor. In most applications, an electrolytic
capacitor of between 47µF and 220µF is also required
across the part, both for filtering and as part of the start-up
bootstrap circuitry.
12
FUNCTIONAL DESCRIPTION
CC
BIAS
=
=
BIAS
regulator, to regulate the voltage supplied to
of 20V, a V
CC
=
< 240Ω
+
+
−
+
−
+
×
CC
+
DC
of 15V and the ML4804
VIN
REF
OSC
I1
L1
U4
=
=
+
–
EA
RAMP
CLK
U3
Figure 5. Typical Leading Edge Control Scheme
Ω
VEAO
SW2
SW1
+
–
CMP
U1
(Continued)
I2
C1
I4
I3
(7)
(8)
D
R
DFF
CLK
U2
RL
Q
Q
LEADING/TRAILING MODULATION
Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will
turn on right after the trailing edge of the system clock.
The error amplifier output voltage is then compared with
the modulating ramp. When the modulating ramp reaches
the level of the error amplifier output voltage, the switch
will be turned OFF. When the switch is ON, the inductor
current will ramp up. The effective duty cycle of the
trailing edge modulation is determined during the ON
time of the switch. Figure 4 shows a typical trailing edge
control scheme.
In the case of leading edge modulation, the switch is
turned OFF right at the leading edge of the system clock.
When the modulating ramp reaches the level of the error
amplifier output voltage, the switch will be turned ON.
The effective duty-cycle of the leading edge modulation
is determined during the OFF time of the switch. Figure 5
shows a leading edge control scheme.
One of the advantages of this control technique is that it
requires only one system clock. Switch 1 (SW1) turns off
and switch 2 (SW2) turns on at the same instant to
minimize the momentary “no-load” period, thus lowering
ripple voltage generated by the switching action. With
such synchronized switching, the ripple voltage of the
first stage is reduced. Calculation and evaluation have
shown that the 120Hz component of the PFC’s output
ripple voltage can be reduced by as much as 30% using
this method.
TYPICAL APPLICATIONS
Figure 6 is the application circuit for a complete 100W
power factor corrected power supply, designed using the
methods and general topology detailed in Application
Note 33.
RAMP
VSW1
VEAO
TIME
TIME
REV. 1.0.2 3/9/2001