ML4804 Fairchild, ML4804 Datasheet - Page 11

• Manufacturer Part Number: ML4804
• Description: Power Factor Correction and PWM Controller Combo
• Manufacturer: Fairchild

FUNCTIONAL DESCRIPTION
No voltage error amplifier is included in the PWM stage of
the ML4804, as this function is generally performed on the
output side of the PWM’s isolation boundary. To facilitate
the design of optocoupler feedback circuitry, an offset has
been built into the PWM’s RAMP 2 input which allows
V
voltages below 1.25V.
PWM Current Limit
The DC I
current limiter for the PWM section. Should the input
voltage at this pin ever exceed 1V, the output of the PWM
will be disabled until the output flip-flop is reset by the
clock pulse at the start of the next PWM power cycle.
V
The V
PFC and inhibits the PWM if this voltage on V
than its nominal 2.45V. Once this voltage reaches 2.45V,
which corresponds to the PFC output capacitor being
charged to its rated boost voltage, the soft-start begins.
PWM Control (RAMP 2)
When the PWM section is used in current mode, RAMP 2
is generally used as the sampling point for a voltage
representing the current in the primary of the PWM’s
output transformer, derived either by a current sensing
resistor or a current transformer. In voltage mode, it is the
input for a ramp voltage generated by a second set of
timing components (R
minimum value of zero volts and should have a peak
value of approximately 5V. In voltage mode operation,
REV. 1.0.2 3/9/2001
DC
IN
OK Comparator
to command a zero percent duty cycle for input
IN
OK comparator monitors the DC output of the
LIMIT
pin is a direct input to the cycle-by-cycle
RAMP2
+
DC
, C
VIN
REF
OSC
RAMP2
I1
L1
U4
+
–
EA
RAMP
CLK
U3
Figure 4. Typical Trailing Edge Control Scheme
), that will have a
SW2
SW1
+
–
(Continued)
U1
FB
I2
is less
C1
I4
I3
D
R
DFF
CLK
U2
RL
Q
Q
feedforward from the PFC output buss is an excellent way
to derive the timing ramp for the PWM stage.
Soft Start
Start-up of the PWM is controlled by the selection of the
external capacitor at SS. A current source of 25µA
supplies the charging current for the capacitor, and start-
up of the PWM begins at 1.25V. Start-up delay can be
programmed by the following equation:
where C
t
It is important that the time constant of the PWM soft-start
allow the PFC time to generate sufficient output power for
the PWM section. The PWM start-up delay should be at
least 5ms.
Solving for the minimum value of C
Caution should be exercised when using this minimum
soft start capacitance value because premature charging of
the SS capacitor and activation of the PWM section can
result if V
comparator at start-up. The magnitude of V
related both to line voltage and nominal PFC output
voltage. Typically, a 1.0µF soft start capacitor will allow
time for V
prior to activation of the PWM section at line voltages
between 90Vrms and 265Vrms.
DELAY
is the desired start-up delay.
SS
=
=
FB
FB
RAMP
VSW1
is the required soft start capacitance, and
is in the hysteresis band of the V
and PFC out to reach their nominal values
VEAO
×
×
µ
µ
=
TIME
TIME
SS
:
FB
ML4804
IN
at start-up is
OK
(6a)
(6)
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