HIP6017BCB Intersil Corporation, HIP6017BCB Datasheet - Page 8

• Manufacturer Part Number: HIP6017BCB
• Description: Advanced PWM and Dual Linear Power Control
• Manufacturer: Intersil Corporation

soft-start interval (T4 in Figure 6). At start-up, this allows
V
Cycling the bias input voltage (+12V
then on resets the counter and the fault latch.
Over-Voltage Protection
During operation, a short on the upper PWM MOSFET (Q1)
causes V
over-voltage threshold of 115% (typical) of DACOUT, the
over-voltage comparator trips to set the fault latch and turns Q2
on as required in order to regulate V
This blows the input fuse and reduces V
raises the FAULT/RT pin close to VCC potential.
A separate over-voltage circuit provides protection during
the initial application of power. For voltages on the VCC pin
below the power-on reset (and above ~4V), V
monitored for voltages exceeding 1.26V. Should VSEN1
exceed this level, the lower MOSFET (Q2) is driven on as
needed to regulate V
Over-Current Protection
All outputs are protected against excessive over-currents.
The PWM controller uses the upper MOSFET’s on-
resistance, r
against shorted outputs. The linear regulator monitors the
current of the integrated power device and signals an over-
current condition for currents in excess of 230mA.
Additionally, both the linear regulator and the linear controller
monitor FB2 and FB3 for under-voltage to protect against
excessive currents.
Figures 8 and 9 illustrate the over-current protection with
an overload on OUT1. The overload is applied at T0 and
the current increases through the output inductor (L
At time T1, the OVER-CURRENT1 comparator trips when
the voltage across Q1 (I
programmed by R
discharges the soft-start capacitor (C
current sink, and increments the counter. C
T2 and initiates a soft-start cycle with the error amplifiers
clamped by soft-start. With OUT1 still overloaded, the
LUV
OC1
OV
OUT2
SS
0.15V
FIGURE 7. FAULT LOGIC - SIMPLIFIED SCHEMATIC
4V
and V
OUT1
+
-
+
-
DS(ON)
OUT3
to increase. When the output exceeds the
CURRENT
UP
LATCH
OVER
OCSET
S
R
to slew up without generating a fault.
to monitor the current for protection
OUT1
Q
POR
D
. This inhibits all outputs,
x r
to 1.26V.
DS(ON)
8
R
COUNTER
OUT1
IN
S
) exceeds the level
SS
on the VCC pin) off
OUT1
to 1.15 x DACOUT.
INHIBIT
) with a 11mA
SS
LATCH
. The fault latch
FAULT
S
R
OUT1
recharges at
Q
is
VCC
OUT1
FAULT
HIP6017B
).
inductor current increases to trip the over-current
comparator. Again, this inhibits all outputs, but the soft-start
voltage continues increasing to 4V before discharging. The
counter increments to 2. The soft-start cycle repeats at T3
and trips the over-current comparator. The SS pin voltage
increases to 4V at T4 and the counter increments to 3. This
sets the fault latch to disable the converter. The fault is
reported on the FAULT/RT pin.
The linear regulator operates in the same way as PWM1 to
over-current faults. Additionally, the linear regulator and
linear controller monitor the feedback pins for an under-
voltage. Should excessive currents cause FB2 or FB3 to fall
below the linear under-voltage threshold, the LUV signal
sets the over-current latch if C
LUV signal during the C
outputs to build above the under-voltage threshold during
normal start-up. Cycling the bias input power off then on
resets the counter and the fault latch.
Resistor R
PWM converter. As shown in Figure 9, the internal 200 A
current sink develops a voltage across R
referenced to V
comparator (OVER-CURRENT1). When the voltage across
the upper MOSFET (V
current comparator trips to set the over-current latch. Both
V
across R
to MOSFET switching. The over-current function will trip at a
peak inductor current (I
The OC trip point varies with MOSFET’s temperature. To
avoid over-current tripping in the normal operating load
I
SET
PEAK
10V
4V
2V
0A
0V
0V
and V
=
OCSET
I
--------------------------------------------------- -
OCSET
OCSET1
FIGURE 8. OVER-CURRENT OPERATION
T0
DS
COUNT
= 1
r
T1
DS ON
IN
are referenced to V
helps V
OVERLOAD
APPLIED
. The DRIVE signal enables the over-current
R
programs the over-current trip level for the
OCSET
DS(ON)
PEAK
SS
OCSET
T2
charge interval allows the linear
) determined by:
) exceeds V
COUNT
SS
track the variations of V
TIME
= 2
REPORTED
is fully charged. Blanking the
IN
FAULT
and a small capacitor
OCSET
SET
T3
, the over-
(V
COUNT
SET
= 3
T4
) that is
IN
due