HIP6017BCB Intersil Corporation, HIP6017BCB Datasheet - Page 7

• Manufacturer Part Number: HIP6017BCB
• Description: Advanced PWM and Dual Linear Power Control
• Manufacturer: Intersil Corporation

Description
Operation
The HIP6017B monitors and precisely controls 3 output
voltage levels (Refer to Figures 1, 2, and 3). It is designed for
microprocessor computer applications with 3.3V and 5V
power and 12V bias input from an ATX power supply. The IC
has one PWM controller, a linear controller, and a linear
regulator. The PWM controller (PWM) is designed to
regulate the microprocessor core voltage (V
controller drives 2 MOSFETs (Q1 and Q2) in a synchronous-
rectified buck converter configuration and regulates the core
voltage to a level programmed by the 5-bit digital-to-analog
converter (DAC). An integrated linear regulator supplies the
2.5V clock generator power (V
drives an external MOSFET (Q3) to supply the GTL bus
power (V
Initialization
The HIP6017B automatically initializes upon receipt of input
power. By the time the soft-start (SS) voltage reaches 4V,
the 3.3V input has to be high enough such that the two linear
outputs (V
threshold. A typical ATX supply meets this requirement. The
Power-On Reset (POR) function continually monitors the
input supply voltages. The POR monitors the bias voltage
(+12V
the OCSET1 pin. The normal level on OCSET1 is equal to
+5V
The POR function initiates soft-start operation after both
input supply voltages exceed their POR thresholds.
Soft-Start
The POR function initiates the soft-start sequence. Initially,
the voltage on the SS pin rapidly increases to approximately
1V (this minimizes the soft-start interval). Then an internal
11 A current source charges an external capacitor (C
the SS pin to 4V. The PWM error amplifier reference input
(+ terminal) and output (COMP1 pin) are clamped to a level
proportional to the SS pin voltage. As the SS pin voltage
slews from 1V to 4V, the output clamp allows generation of
PHASE pulses of increasing width that charge the output
capacitor(s). After this initial stage, the reference input clamp
slows the output voltage rate-of-rise and provides a smooth
transition to the final set voltage. Additionally, both linear
regulator’s reference inputs are clamped to a voltage
proportional to the SS pin voltage. This method provides a
rapid and controlled output voltage rise.
Figure 6 shows the soft-start sequence for the typical
application. At T0 the SS voltage rapidly increases to
approximately 1V. At T1, the SS pin and error amplifier
output voltage reach the valley of the oscillator’s triangle
wave. The oscillator’s triangular waveform is compared to
the clamped error amplifier output voltage. As the SS pin
voltage increases, the pulse-width on the PHASE pin
increases. The interval of increasing pulse-width continues
IN
IN
less a fixed voltage drop (see over-current protection).
) at the VCC pin and the 5V input voltage (+5V
OUT3
OUT2
).
, V
OUT3
) have exceeded their under-voltage
7
OUT2
). The linear controller
OUT1
). PWM
SS
IN
) on
) at
HIP6017B
until each output reaches sufficient voltage to transfer
control to the input reference clamp. If we consider the 2.0V
output (V
the interval between T2 and T3, the error amplifier reference
ramps to the final value and the converter regulates the
output to a voltage proportional to the SS pin voltage. At T3
the input clamp voltage exceeds the reference voltage and
the output voltage is in regulation.
The remaining outputs are also programmed to follow the SS
pin voltage. Each linear output (V
follows a ramp similar to that of the PWM output. When each
output reaches sufficient voltage the input reference clamp
slows the rate of output voltage rise. The PGOOD signal
toggles ‘high’ when all output voltage levels have exceeded
their under-voltage levels. See the Soft-Start Interval section
under Applications Guidelines for a procedure to determine
the soft-start interval.
Fault Protection
All three outputs are monitored and protected against
extreme overload. A sustained overload on any linear
regulator output or an over-voltage on the PWM output
disables all converters and drives the FAULT/RT pin to VCC.
Figure 7 shows a simplified schematic of the fault logic. An
over-voltage detected on VSEN1 immediately sets the fault
latch. A sequence of three over-current fault signals also
sets the fault latch. A comparator indicates when C
charged (UP signal), such that an under-voltage event on
either linear output (FB2 or FB3) is ignored until after the
0V
0V
0V
VOLTAGES
(0.5V/DIV)
OUTPUT
OUT1
T0
T1
SOFT-START
FIGURE 6. SOFT-START INTERVAL
) in Figure 6, this time occurs at T2. During
PGOOD
(2V/DIV)
(1V/DIV)
T2
TIME
T3
OUT2
and V
V
OUT1
V
V
OUT3
OUT2
OUT3
(DAC = 2V)
( = 2.5V)
( = 1.5V)
SS
) initially
T4
is fully