AT28C17-15 ATMEL Corporation, AT28C17-15 Datasheet - Page 3

• Manufacturer Part Number: AT28C17-15
• Description: 16K 2K x 8 CMOS E2PROM
• Manufacturer: ATMEL Corporation

Device Operation
READ: The AT28C17 is accessed like a Static RAM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in a high im-
pedance state whenever CE or OE is high. This dual line
control gives designers increased flexibility in preventing
bus contention.
BYTE WRITE: Writing data into the AT28C17 is similar to
writing into a Static RAM. A low pulse on the WE or CE
input with OE high and CE or WE low (respectively) initi-
ates a byte write. The address location is latched on the
last falling edge of WE (or CE); the new data is latched on
the first rising edge. Internally, the device performs a self-
clear before write. Once a byte write has been started, it
will automatically time itself to completion. Once a pro-
gramming operation has been initiated and for the dura-
tion of t
operation.
FAST BYTE WRITE: The AT28C17E offers a byte write
time of 200 s maximum. This feature allows the entire
device to be rewritten in 0.4 seconds.
READY/BUSY: Pin 1 is an open drain READY/BUSY
output that can be used to detect the end of a write cycle.
RDY/BUSY is actively pulled low during the write cycle
and is released at the completion of the write. The open
drain connection allows for OR-tying of several devices to
the same RDY/BUSY line.
WC
, a read operation will effectively be a polling
DATA POLLING: The AT28C17 provides DATA POLL-
ING to signal the completion of a write cycle. During a
write cycle, an attempted read of the data being written
results in the complement of that data for I/O
outputs are indeterminate). When the write cycle is fin-
ished, true data appears on all outputs.
WRITE PROTECTION: Inadvertent writes to the device
are protected against in the following ways. (a) V
sense— if V
inhibited. (b) V
reached 3.8V the device will automatically time out 5 ms
(typical) before allowing a byte write. (c) Write Inhibit—
holding any one of OE low, CE high or WE high inhibits
byte write cycles.
CHIP CLEAR: The contents of the entire memory of the
AT28C17 may be set to the high state by the CHIP CLEAR
operation. By setting CE low and OE to 12 volts, the chip
is cleared when a 10 msec low pulse is applied to WE.
DEVICE IDENTIFICATION: A n e x t r a 3 2 - b y t e s o f
E
identification. By raising A9 to 12
dress locations 7E0H to 7FFH the additional bytes may be
written to or read from in the same manner as the regular
memory array.
2
PROM memory are available to the user for device
CC
is below 3.8V (typical) the write function is
CC
power on delay— once V
AT28C17
0.5V and using ad-
7
(the other
CC
2-185
h a s
CC