HT82J97A_08 HOLTEK [Holtek Semiconductor Inc], HT82J97A_08 Datasheet - Page 10

• Manufacturer Part Number: HT82J97A_08
• Description: USB Joystick Encoder 8-Bit MCU
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

tem clock divided by 4), determine by ROM code option.
This timer is designed to prevent a software malfunction
or sequence from jumping to an unknown location with
unpredictable results. The Watchdog Timer can be dis-
abled by ROM code option. If the Watchdog Timer is dis-
abled, all the executions related to the WDT result in no
operation.
Once the internal WDT oscillator (RC oscillator with a
period of 31 s/5V normally) is selected, it is first divided
by 256 (8-stage) to get the nominal time-out period of
8ms/5V. This time-out period may vary with tempera-
tures, VDD and process variations. By invoking the
WDT prescaler, longer time-out periods can be realized.
Writing data to WS2, WS1, WS0 (bits 2, 1, 0 of the
WDTS) can give different time-out periods. If WS2,
WS1, and WS0 are all equal to 1, the division ratio is up
to 1:128, and the maximum time-out period is 1s/5V. If
the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operates in the
same manner except that in the HALT state the WDT
may stop counting and lose its protecting purpose. In
this situation the logic can only be restarted by external
logic. The high nibble and bit 3 of the WDTS are re-
served for user defined flags, which can only be set to
If the device operates in a noisy environment, using the
on-chip 32kHz RC oscillator (WDT OSC) is strongly rec-
ommended, since the HALT will stop the system clock.
The WDT overflow under normal operation will initialize
a chip reset and set the status bit TO . But in the
HALT mode, the overflow will initialize a warm reset
and only the program counter and SP are reset to zero.
To clear the contents of the WDT (including the WDT
prescaler), three methods are adopted; external reset (a
Rev. 1.60
10000 (WDTS.7~WDTS.3).
WS2
0
0
0
0
1
1
1
1
WS1
0
0
1
1
0
0
1
1
WDTS (09H) Register
WS0
0
1
0
1
0
1
0
1
Division Ratio
1:128
1:16
1:32
1:64
1:1
1:2
1:4
1:8
Watchdog Timer
10
low level to RES), software instruction and a HALT in-
struction. The software instruction include CLR WDT
and the other set
these two types of instruction, only one can be active de-
pending on the ROM code option
lection option . If the CLR WDT is selected (i.e.
CLRWDT times is equal to one), any execution of the
that CLR WDT and CLR WDT are chosen (i.e.
CLRWDT times is equal to two), these two instructions
must be executed to clear the WDT; otherwise, the WDT
may reset the chip as a result of time-out.
Power Down Operation - HALT
The HALT mode is initialized by the HALT instruction
and results in the following:
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow per-
forms a warm reset . After the TO and PDF flags are
examined, the cause for chip reset can be determined.
The PDF flag is cleared by a system power-up or exe-
cuting the CLR WDT instruction and is set when exe-
cuting the HALT instruction. The TO flag is set if the
WDT time-out occurs, and causes a wake-up that only
resets the program counter and SP; the others remain in
their original status.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake-up the
device by mask option. Awakening from an I/O port stim-
ulus, the program will resume execution of the next in-
struction. If it awakens from an interrupt, two sequence
may occur. If the related interrupt is disabled or the inter-
rupt is enabled but the stack is full, the program will re-
CLR WDT instruction will clear the WDT. In the case
The system oscillator will be turned off but the WDT
oscillator remains running (if the WDT oscillator is se-
lected).
The contents of the on-chip RAM and registers remain
unchanged.
The WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT os-
cillator).
All of the I/O ports remain in their original status.
The PDF flag is set and the TO flag is cleared.
CLR WDT1 and CLR WDT2 . Of
HT82J97E/HT82J97A
December 23, 2008
CLR WDT times se-