XR20V2172IL64 EXAR [Exar Corporation], XR20V2172IL64 Datasheet
XR20V2172IL64
Related parts for XR20V2172IL64
XR20V2172IL64 Summary of contents
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TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER FEBRUARY 2007 GENERAL DESCRIPTION 1 The XR20V2172 (V2172 high performance two channel universal asynchronous transmitter (UART) with 64 byte TX and RX FIFOs selectable I C/SPI ...
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... CTSB 4 RTSB 5 RXB_SEL 6 RXB 7 TXB 8 N.C. 9 N.C. 10 N.C. 11 DTRB 12 RIB 13 DSRB 14 XTAL1 15 GND 16 ORDERING INFORMATION ART UMBER XR20V2172IL64 64-pin QFN PRELIMINARY XR20V2172 64-pin QFN O T ACKAGE PERATING EMPERATURE -40°C to +85°C 2 REV. P1.0.1 48 N.C. 47 N.C. 46 N.C. 45 VCC 44 C2+ 43 C2- 42 TXDA DTRA 41 DSRA 40 RXDA ...
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TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER REV. P1.0.1 PIN DESCRIPTIONS Pin Description 64-QFN N AME I2C (SPI) INTERFACE C/SPI# SDA 2 SCK 33 A0/ 57 CS# A1 ...
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XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER Pin Description 64-QFN N AME DTRA 12 DTRB 40 DSRA 14 DSRB 60 CDA 62 CDB 58 RIA 13 RIB Ancillary signals (CMOS/TTL Voltage Levels) ...
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TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER REV. P1.0.1 Pin Description 64-QFN N AME 10, 11, 18, 22, 23, 26, 30, 31, 32, 34, 35, 37, 46, 47, 48, 49, 55 ...
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XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER 1.0 PRODUCT DESCRIPTION The XR20V2172 (V2172) integrates a selectable I Universal Asynchronous Receiver and Transmitter (UART) and an RS-232 Transceiver. The configuration registers set is 16550 UART compatible for ...
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TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER REV. P1.0.1 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The V2172 can operate with either an I the I2C/SPI# input pin. The V2172 can operate with either an I interface is ...
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XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER IGURE ATA ORMATS SLAVE Master write: ADDRESS START condition write acknowledge SLAVE Master read: ADDRESS START ...
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TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER REV. P1.0.1 2 2.2 I C-bus Addressing There could be many devices on the I are eight possible slave addresses that can be selected for the V2172 using the A1 ...
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XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER 2.2.1 SPI Bus Interface The SPI interface consists of four lines: serial clock (SCL), chip select (CS#), slave output (SO) and slave input (SI). The serial clock, slave output ...
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TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER REV. P1.0.1 T ABLE FCR (FIFO D ISABLED IRQ# Pin HIGH = no data LOW = 1 byte 2.6 Crystal Oscillator or External Clock Input ...
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XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER value of ’1’ (DLL = 0x01, DLM = 0x00 and DLD = 0x00) upon reset. Therefore, the BRG must be programmed during initialization to the operating data rate. The ...
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TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER REV. P1.0 ABLE YPICAL DATA RATES WITH A Required D IVISOR FOR Output Data 16x Clock O Rate (Decimal) 400 3750 2400 625 4800 312.5 9600 156.25 ...
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XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER 2.8.2 Transmitter Operation in non-FIFO Mode The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the data ...
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TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER REV. P1.0.1 2.9 Receiver The receiver section contains an 8-bit Receive Shift Register (RSR) and 64 bytes of FIFO which includes a byte-wide Receive Holding Register (RHR). The RSR uses ...
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XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER F 12 IGURE ECEIVER PERATION IN 16X Clock ( DLD[5:4] ) Receive Data Shift Register (RSR) 64 bytes by 11-bit wide FIFO Data ...
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TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER REV. P1.0.1 the stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input is re- asserted (LOW), indicating more data may be sent. ...
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XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER 2.13 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, ...
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TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER REV. P1.0.1 The V2172 UART portion stops its crystal oscillator to conserve power in this mode. The user can check the XTAL2 pin for no clock output as an indication ...
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XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER 2.16 Internal Loopback The V2172 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. ...
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TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER REV. P1.0.1 3.0 UART INTERNAL REGISTERS The complete register set is shown below UART INTERNAL REGISTER ADDRESSES ABLE A DDRESS 0X00 RHR - Receive Holding Register THR ...
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XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER . T 8: INTERNAL REGISTERS DESCRIPTION. ABLE EAD DDR AME RITE 0x00 RHR RD Bit-7 0x00 THR WR Bit-7 ...
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TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER REV. P1.0 INTERNAL REGISTERS DESCRIPTION. ABLE EAD DDR AME RITE 0x0A IODir RD/WR Bit-7 0x0B IOState RD/WR Bit-7 ...
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XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER 4.3.1 IER versus Receive FIFO Interrupt Mode Operation When the receive FIFO (FCR BIT and receive interrupts (IER BIT are enabled, the RHR interrupts (see ...
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TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER REV. P1.0.1 IER[4]: Sleep Mode Enable (requires EFR bit • Logic 0 = Disable Sleep Mode (default). • Logic 1 = Enable Sleep Mode. See Sleep Mode section ...
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XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER • Special character interrupt is cleared by a read to ISR. • RTS# and CTS# flow control interrupts are cleared by a read to the MSR register ...
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TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER REV. P1.0.1 FCR[1]: RX FIFO Reset This bit is only active when FCR bit ‘1’. • Logic receive FIFO reset (default) • Logic 1 = ...
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XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER 4.6 Line Control Register (LCR) - Read/Write The Line Control Register is used to specify the asynchronous data communication format. The word or character length, the number of stop ...
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TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER REV. P1.0.1 LCR[5]: TX and RX Parity Select If the parity bit is enabled, LCR BIT-5 selects the forced parity format. • LCR BIT-5 = logic 0, parity is not ...
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XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER MCR[2]: OP1# / TCR and TLR Enable OP1# is not available as an output pin on the V2172. But it is available for use during Internal Loopback Mode (MCR[4] ...
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TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER REV. P1.0.1 4.8 Line Status Register (LSR) - Read Only This register provides the status of data transfers between the UART and the host. LSR[0]: Receive Data Ready Indicator • ...
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XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER MSR[0]: Delta CTS# Input Flag • Logic change on CTS# input (default). • Logic 1 = The CTS# input has changed state since the last time ...
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TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER REV. P1.0.1 TCR[3:0]: RX FIFO Halt Level A value of 0-60 (decimal value of TCR[3:0] multiplied by 4) can be selected as the Halt Level. When the RX FIFO is ...
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XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER 4.17 GPIO Interrupt Enable Register (IOIntEna) - Read/Write This register enables the interrupt for the GPIO pins. The interrupts for GPIO[7:4] are only enabled if IOControl[ ...
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TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER REV. P1.0.1 EFCR[1] = Receiver Disable UART will stop receiving data immediately once this bit is set to a Logic 1. Any data that is being received in the TSR ...
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XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER EFR[3:0]: Software Flow Control Select Single character and dual sequential characters software flow control is supported. Combinations of software flow control can be selected by programming these bits. T ...
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TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER REV. P1.0.1 EFR[6]: Auto RTS Flow Control Enable RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is selected, an ...
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XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER REGISTERS DLM, DLL DLD RHR THR IER FCR ISR LCR MCR LSR MSR SPR TCR TLR TXLVL RXLVL IODir IOState IOIntEna IOCont EFCR EFR XON1 XON2 XOFF1 XOFF2 I/O ...
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TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER REV. P1.0.1 5.0 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA ( Thermal Resistance (64-QFN) ...
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XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER ELECTRICAL CHARACTERISTICS 85, V NLESS OTHERWISE NOTED P SYMBOL ARAMETER DC C HARACTERISTICS I Supply Current, Normal Mode CC I Supply Current, ...
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TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER REV. P1.0.1 AC ELECTRICAL CHARACTERISTICS - UART CLOCK o Unless otherwise noted: TA=-40 to +85 S YMBOL XTAL1 UART Crystal Oscillator ECLK UART External Clock T External Clock Time Period ...
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XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER AC ELECTRICAL CHARACTERISTICS - I2C-BUS TIMING SPECIFICATIONS o Unless otherwise noted: TA=- YMBOL f Operating frequency SCL T Bus free time between STOP and START ...
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TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER REV. P1.0.1 F 16. SCL IGURE ELAY FTER ESET RESET# SCL 2 F 17 IGURE US IMING IAGRAM START Protocol condition (S) T ...
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XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER F 19 IGURE ODEM NPUT IN NTERRUPT SLAVE SDA W ADDRESS IRQ MODEM pin F 20. GPIO P I IGURE IN NTERRUPT SLAVE ...
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TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER REV. P1.0 IGURE ECEIVE NTERRUPT Start bit RX D0 IRQ IGURE ECEIVE NTERRUPT LEAR SLAVE SDA W A ADDRESS IRQ# F ...
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XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER AC ELECTRICAL CHARACTERISTICS - SPI-BUS TIMING SPECIFICATIONS o Unless otherwise noted: TA=- YMBOL T CS# HIGH to SO three-state time TR T CS# to SCL ...
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TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER REV. P1.0.1 F 25. SPI W MCR DTR O IGURE RITE TO CS# SCLK SI R GPIOx F 26. SPI W MCR DTR O IGURE RITE TO ...
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XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER F 27. SPI W THR C IGURE RITE TO LEAR CS# SCLK SI R GPIOx IRQ# F 28. R MSR C M IGURE EAD TO LEAR ...
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TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER REV. P1.0.1 F 29. R IOS C IGURE EAD TATE TO LEAR CS# SCLK SI R IRQ# F 30. R RHR C RX INT IGURE EAD ...
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XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER PACKAGE DIMENSIONS (64 PIN QFN - 0.9 Note: The control dimension is in millimeter. SYMBOL PRELIMINARY ) ...
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TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER REV. P1.0.1 REVISION HISTORY D R ATE EVISION February 2007 P1.0.0 Preliminary Datasheet. February 2007 P1.0.1 VCC range updated to +3.3 to +5.5V. EXAR Corporation reserves the right to make ...