XR16M2551IL32 EXAR [Exar Corporation], XR16M2551IL32 Datasheet - Page 28

• Manufacturer Part Number: XR16M2551IL32
• Description: HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE
• Manufacturer: EXAR [Exar Corporation]

XR16M2551
HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE
]
ISR[0]: Interrupt Status
•
•
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source
Table
ISR[4]: Xoff/Xon or Special Character Interrupt Status
This bit is enabled when EFR bit-4 is set to HIGH. ISR bit-4 indicates that the receiver detected a data match of
the Xoff character(s). If this is an Xoff/Xon interrupt, it can be cleared by a read to the ISR. If it is a special
character interrupt, it can be cleared by reading ISR or it will automatically clear after the next character is
received.
ISR[5]: RTS#/CTS# Interrupt Status
This bit is enabled when EFR bit-4 is set to HIGH. ISR bit-5 indicates that the CTS# or RTS# has been de-
asserted.
ISR[7:6]: FIFO Enable Status
These bits are set to LOW when the FIFOs are disabled. They are set to HIGH when the FIFOs are enabled.
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[0]: TX and RX FIFO Enable
•
•
4.5
P
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending (default condition) or the device has come out of sleep mode.
Logic 0 = Disable the transmit and receive FIFO (default).
Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to HIGH when other FCR bits are
written or they will not be programmed.
RIORITY
L
EVEL
1
2
3
4
5
6
7
-
11).
FIFO Control Register (FCR) - Write-Only
B
IT
0
0
0
0
0
0
1
0
-5
B
IT
0
0
0
0
0
1
0
0
-4
ISR R
B
T
EGISTER
IT
0
1
0
0
0
0
0
0
ABLE
-3
11: I
B
S
IT
TATUS
1
1
1
0
0
0
0
0
-2
NTERRUPT
B
B
ITS
IT
1
0
0
1
0
0
0
0
-1
S
OURCE AND
28
B
IT
0
0
0
0
0
0
0
1
-0
LSR (Receiver Line Status Register)
RXRDY (Receive Data Time-out)
RXRDY (Received Data Ready)
TXRDY (Transmit Ready)
MSR (Modem Status Register)
RXRDY (Received Xoff or Special character)
CTS#, RTS# change of state
None (default) or Wake-up Indicator
P
RIORITY
L
EVEL
S
OURCE OF INTERRUPT
REV. 1.0.2