XR16M2551IL32 EXAR [Exar Corporation], XR16M2551IL32 Datasheet - Page 10

• Manufacturer Part Number: XR16M2551IL32
• Description: HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE
• Manufacturer: EXAR [Exar Corporation]

XR16M2551
HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE
The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A/B and TXRDY# A/B output pins. The transmit and receive FIFO trigger levels provide additional
flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is
empty or has an empty location(s) for more data. The user can optionally operate the transmit and receive
FIFO in the DMA mode (FCR bit-3=1). When the transmit and receive FIFO are enabled and the DMA mode is
disabled (FCR bit-3 = 0), the M2551 is placed in single-character mode for data transmit or receive operation.
When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by loading or
unloading the FIFO in a block sequence determined by the selected trigger level. In this mode, the M2551 sets
the TXRDY# pin when the transmit FIFO becomes full, and sets the RXRDY# pin when the receive FIFO
becomes empty. The following table shows their behavior. Also see
The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup.
Table 4 and 5
through
2.6
2.7
RXRDY# A/B LOW = 1 byte
TXRDY# A/B LOW = THR empty
INTA/B Pin
INTA/B Pin
P
INS
DMA Mode
INTA and INTB Outputs
24.
HIGH = No data
HIGH = Byte in THR
summarize the operating behavior for the transmitter and receiver. Also see
LOW = A byte in THR
HIGH = THR empty
LOW = No data
HIGH = 1 byte
(FIFO D
FCR
T
ABLE
BIT
T
(FIFO D
(FIFO D
ISABLED
ABLE
FCR B
FCR B
-0 = 0
T
3: TXRDY#
ABLE
4: INTA
)
IT
ISABLED
IT
ISABLED
-0 = 0
5: INTA
-0 = 0
LOW = At least 1 byte in FIFO
HIGH = FIFO empty
LOW = FIFO empty
HIGH = At least 1 byte in FIFO
)
)
AND
AND
(DMA M
AND
INTB P
RXRDY# O
FCR
INTB P
ODE
LOW = FIFO above trigger level
HIGH = FIFO below trigger level or FIFO empty
LOW = FIFO below trigger level
HIGH = FIFO above trigger level
BIT
INS
-3 = 0
D
10
ISABLED
IN
O
UTPUTS IN
O
PERATION FOR
PERATION
FCR
)
BIT
FCR B
FIFO
HIGH to LOW transition when FIFO reaches the
trigger level, or time-out occurs
LOW to HIGH transition when FIFO empties
LOW = FIFO has at least 1 empty location
HIGH = FIFO is full
-0 = 1 (FIFO E
Figures 19
F
OR
IT
T
(FIFO E
AND
RANSMITTER
-0 = 1 (FIFO E
R
FCR B
ECEIVER
DMA M
(DMA M
IT
NABLED
through 24.
NABLED
-0 = 1
FCR
ODE
ODE
NABLED
)
BIT
)
-3 = 1
E
NABLED
)
)
Figures 19
REV. 1.0.2