W78E52BF-40 WINBOND [Winbond], W78E52BF-40 Datasheet - Page 7

• Manufacturer Part Number: W78E52BF-40
• Description: 8-BIT MTP MICROCONTROLLER
• Manufacturer: WINBOND [Winbond]

The power-off flag is located at PCON.4. This bit is set when V
be used to determine if a reset is a warm boot or a cold boot if it is subsequently reset by software.
Watchdog Timer
The Watchdog timer is a free-running timer which can be programmed by the user to serve as a
system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide
the system clock. The divider output is selectable and determines the time-out interval. When the
time-out occurs a system reset can also be caused if it is enabled. The main use of the Watchdog
timer is as a system monitor. This is important in real-time control applications. In case of power
glitches or electro-magnetic interference, the processor may begin to execute errant code. If this is
left unchecked the entire system may crash. The watchdog time-out selection will result in different
time-out values depending on the clock speed. The Watchdog timer will de disabled on reset. In
general, software should restart the Watchdog timer to put it into a known state. The control bits that
support the Watchdog timer are discussed below.
Watchdog Timer Control Register
ENW : Enable watch-dog if set.
CLRW : Clear watch-dog timer and prescaler if set. This flag will be cleared automatically
WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled
PS2, PS1, PS0 : Watch-dog prescaler timer select. Prescaler is selected when set PS2~0 as follows:
The time-out period is obtained using the following equation:
OSC
1
2
under IDLE mode. Default is cleared.
14
PRESCALER 1000 12 mS
Bit:
PS2 PS1 PS0
0
0
0
0
1
1
1
1
0
1
0
1
0
0
1
1
ENW
Mnemonic: WDTC
7
0
0
1
1
0
1
0
1
CLRW
6
PRESCALER SELECT
WIDL
- 7 -
5
128
256
16
32
64
2
4
8
Address: 8FH
4
-
Preliminary W78E52B
Publication Release Date: December 1998
DD
has been applied to the part. It can
3
-
PS2
2
PS1
1
Revision A1
PS0
0