W78E52BF-40 WINBOND [Winbond], W78E52BF-40 Datasheet - Page 5

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W78E52BF-40

Manufacturer Part Number
W78E52BF-40
Description
8-BIT MTP MICROCONTROLLER
Manufacturer
WINBOND [Winbond]
Datasheets
The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a special feature
of the W78E54B: it is a 16-bit timer/counter that is configured and controlled by the T2CON register.
Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer,
depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-
reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that
of Timers 0 and 1.
New Defined Peripheral
In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupt
1. INT2 / INT3
Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register
is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To
set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example,
"SETB 0C2H" sets the EX2 bit of XICON.
XICON - external interrupt control (C0H)
PX3: External interrupt 3 priority high if set
EX3: External interrupt 3 enable if set
IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced
IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software
PX2: External interrupt 2 priority high if set
EX2: External interrupt 2 enable if set
IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced
IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software
Eight-source interrupt informations:
INT2 , INT3 has been added to either the PLCC or QFP 44 pin package. And description follows:
External Interrupt 0
Timer/Counter 0
External Interrupt 1
Timer/Counter 1
Serial Port
Timer/Counter 2
External Interrupt 2
External Interrupt 3
PX3
INTERRUPT
SOURCE
EX3
IE3
ADDRESS
VECTOR
0BH
1BH
2BH
3BH
03H
13H
23H
33H
IT3
SEQUENCE WITHIN
0 (highest)
1
2
3
4
5
6
7 (lowest)
PRIORITY LEVEL
POLLING
PX2
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EX2
Preliminary W78E52B
Publication Release Date: December 1998
IE.0
IE.1
IE.2
IE.3
IE.4
IE.5
XICON.2
XICON.6
REQUIRED
SETTINGS
ENABLE
IE2
IT2
EDGE/LEVEL
INTERRUPT
XICON.0
XICON.3
TCON.0
TCON.2
TYPE
Revision A1
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