LM3S600-IQC20-A0T BOOKHAM [Bookham, Inc.], LM3S600-IQC20-A0T Datasheet - Page 17
LM3S600-IQC20-A0T
Manufacturer Part Number
LM3S600-IQC20-A0T
Description
Microcontroller
Manufacturer
BOOKHAM [Bookham, Inc.]
Datasheet
1.LM3S600-IQC20-A0T.pdf
(378 pages)
- Current page: 17 of 378
- Download datasheet (4Mb)
1
1.1
October 01, 2007
Architectural Overview
The Luminary Micro Stellaris
controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller
applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to
legacy 8- and 16-bit devices, all in a package with a small footprint.
The LM3S600 microcontroller is targeted for industrial applications, including test and measurement
equipment, factory automation, HVAC and building control, motion control, medical instrumentation,
fire and security, and power/energy.
In addition, the LM3S600 microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, the LM3S600 microcontroller is code-compatible
to all members of the extensive Stellaris
needs.
Luminary Micro offers a complete solution to get to market quickly, with evaluation and development
boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong
support, sales, and distributor network.
Product Features
The LM3S600 microcontroller includes the following product features:
■
■
32-Bit RISC Performance
–
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–
–
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Internal Memory
32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded
applications
System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero
counter with a flexible control mechanism
Thumb®-compatible Thumb-2-only instruction set processor core for high code density
50-MHz operation
Hardware-division and single-cycle-multiplication
Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt
handling
21 interrupts with eight priority levels
Memory protection unit (MPU), providing a privileged mode for protected operating system
functionality
Unaligned data access, enabling data to be efficiently packed into memory
Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
®
family of microcontrollers—the first ARM® Cortex™-M3 based
Preliminary
®
family; providing flexibility to fit our customers' precise
LM3S600 Microcontroller
17
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