LM3S600-IQC20-A0T BOOKHAM [Bookham, Inc.], LM3S600-IQC20-A0T Datasheet - Page 116
LM3S600-IQC20-A0T
Manufacturer Part Number
LM3S600-IQC20-A0T
Description
Microcontroller
Manufacturer
BOOKHAM [Bookham, Inc.]
Datasheet
1.LM3S600-IQC20-A0T.pdf
(378 pages)
- Current page: 116 of 378
- Download datasheet (4Mb)
Internal Memory
USec Reload (USECRL)
Base 0x400F.E000
Offset 0x140
Type R/W, reset 0x31
116
Reset
Reset
Type
Type
Bit/Field
31:8
7:0
RO
RO
31
15
0
0
Register 7: USec Reload (USECRL), offset 0x140
Note:
This register is provided as a means of creating a 1-μs tick divider reload value for the flash controller.
The internal flash has specific minimum and maximum requirements on the length of time the high
voltage write pulse can be applied. It is required that this register contain the operating frequency
(in MHz -1) whenever the flash is being erased or programmed. The user is required to change this
value if the clocking conditions are changed for a flash erase/program operation.
RO
RO
30
14
0
0
reserved
Name
USEC
Offset is relative to System Control base address of 0x400F.E000
RO
RO
29
13
0
0
RO
RO
28
12
0
0
reserved
RO
RO
Type
27
11
R/W
0
0
RO
RO
RO
26
10
0
0
Reset
0x00
0x31
RO
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Microsecond Reload Value
MHz -1 of the controller clock when the flash is being erased or
programmed.
USEC should be set to 0x31 (50 MHz) whenever the flash is being erased
or programmed.
RO
RO
24
0
8
0
reserved
R/W
RO
23
0
7
0
R/W
RO
22
0
6
0
R/W
RO
21
0
5
1
R/W
RO
20
0
4
1
USEC
R/W
RO
19
0
3
0
R/W
RO
18
0
2
0
October 01, 2007
R/W
RO
17
0
1
0
R/W
RO
16
0
0
1
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