ATTINY15 ATMEL [ATMEL Corporation], ATTINY15 Datasheet - Page 22

• Manufacturer Part Number: ATTINY15
• Manufacturer: ATMEL [ATMEL Corporation]

The MCU Control Register –
MCUCR
22
ATtiny15L
one CPU clock period will generate an interrupt. Shorter pulses are not guaranteed to
generate an interrupt.
The MCU Control Register contains control bits for general MCU functions.
• Bits 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny15L and always reads as zero.
• Bit 6- PUD: Pull-up Disable
This PUD bit must be set (one) to disable internal pull-up registers at Port B.
• Bit 5 – SE: Sleep Enable
The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the pro-
grammer’s purpose, it is recommended to set the Sleep Enable SE bit just before the
execution of the SLEEP instruction.
• Bits 4, 3 – SM1, SM0: Sleep Mode Select Bits 1 and 0
These bits select between the three available sleep modes, as shown in Table 7.
Table 7. Sleep Modes
For details, refer to “Sleep Modes” below.
• Bit 2 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny15L and always reads as zero.
• Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the
corresponding interrupt mask is set (one). The activity on the external INT0 pin that acti-
vates the interrupt is defined in Table 8:
Table 8. Interrupt 0 Sense Control
Note:
Bit
$35
Read/Write
Initial Value
ISC01
SM1
0
0
1
1
0
0
1
1
1. When changing the ISC10/ISC00 bits, INT0 must be disabled by clearing its Interrupt
Enable bit in the GIMSK register. Otherwise an interrupt can occur when the bits are
changed.
R
7
–
0
SM0
ISC00
0
1
0
1
0
1
0
1
PUD
R/W
6
0
Sleep Mode
Idle mode
ADC Noise Reduction mode
Power-down mode
Reserved
Description
The low level of INT0 generates an interrupt request.
Any change on INT0 generates an interrupt request
The falling edge of INT0 generates an interrupt request.
The rising edge of INT0 generates an interrupt request.
R/W
SE
5
0
(1)
SM1
R/W
4
0
SM0
R/W
3
0
R
2
–
0
ISC01
R/W
1
0
ISC00
R/W
0
0
1187D–12/01
MCUCR