ATTINY15 ATMEL [ATMEL Corporation], ATTINY15 Datasheet - Page 19

• Manufacturer Part Number: ATTINY15
• Manufacturer: ATMEL [ATMEL Corporation]

Interrupt Response Time
The General Interrupt Mask
Register – GIMSK
The General Interrupt Flag
Register – GIFR
1187D–12/01
Note that the Status Register is not automatically stored when entering an interrupt rou-
tine and restored when returning from an interrupt routine. This must be handled by
software.
The interrupt execution response for all the enabled AVR interrupts is four clock cycles
minimum. After the four clock cycles the program vector address for the actual interrupt
handling routine is executed. During this 4-clock-cycle period, the Program Counter (9
bits) is pushed onto the Stack. The vector is often a relative jump to the interrupt routine,
and this jump takes two clock cycles. If an interrupt occurs during execution of a multi-
cycle instruction, this instruction is completed before the interrupt is served . If an inter-
rupt occurs when the MCU is in Sleep mode, the interrupt execution response time is
increased by four clock cycles.
A return from an interrupt handling routine takes four clock cycles. During these four
clock cycles, the Program Counter (9 bits) is popped back from the Stack. When AVR
exits from an interrupt, it will always return to the main program and execute one more
instruction before any pending interrupt is served.
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny15L and always reads as zero.
• Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is activated. The Interrupt Sense Control0 bits 1/0 (ISC01 and
ISC00) in the MCU general Control Register (MCUCR) define whether the external
interrupt is activated on rising or falling edge, on pin change, or low level of the INT0 pin.
Activity on the pin will cause an interrupt request even if INT0 is configured as an output.
The corresponding interrupt of External Interrupt Request 0 is executed from program
memory address $001. See also “External Interrupts.”
• Bit 5 – PCIE: Pin Change Interrupt Enable
When the PCIE bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the interrupt on pin change is enabled. Any change on any input or I/O pin will cause an
interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from
program memory address $002. See also “Pin Change Interrupt.”
• Bits 4..0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny15L and always read as zero.
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny15L and always reads as zero.
Bit
$3B
Read/Write
Initial Value
Bit
$3A
Read/Write
Initial Value
R
R
7
–
0
7
–
0
INTF0
INT0
R/W
R/W
6
0
6
0
PCIE
PCIF
R/W
R/W
5
0
5
0
R
R
4
–
0
4
–
0
R
R
3
–
0
3
–
0
2
–
R
0
2
–
R
0
R
R
1
–
0
1
–
0
ATtiny15L
R
R
0
–
0
0
–
0
GIMSK
GIFR
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