TMP47C990E TOSHIBA [Toshiba Semiconductor], TMP47C990E Datasheet - Page 8

• Manufacturer Part Number: TMP47C990E
• Description: CMOS 4-bit Microcontroller
• Manufacturer: TOSHIBA [Toshiba Semiconductor]

TMP47C101/201
8/32
(1)
(2)
Stack
The stack provides the area in which the return
address is saved before a jump is performed to the
processing routine at the execution of a subroutine call
instruction or the acceptance of an interrupt. When a
subroutine call instruction is executed, the contents
(the return address) of the program counter are saved;
when an interrupt is accepted, the contents of the pro-
gram counter and flags are saved.
When returning from the processing routine, executing
the subroutine return instruction [RET] restores the
contents of the program counter from the stack; exe-
cuting the interrupt return instruction [RETI] restores
the contents of the program counter and flags.
The stack consists of up to 15 levels (locations 0
through 14) which are provided in the data memory
(addresses 40
of 4-word data memory. Locations 13 and 14 are
shared with the count registers of the timer/counters
(TC1, TC2) to be described later.
The save/restore locations in the stack are determined
by the stack pointer word (SPW). The SPW is automat-
ically decremented after save, and incremented before
restore.That is, the value of the SPW indicates the
stack location number for the next save.
Stack Pointer Word (SPW)
Address 7F
is called the stack pointer word, which identifies the
location in the stack to be accessed (save or restore).
Generally, location number 0 to 12 can be set to the
SPW, providing up to 13 levels of stack nesting. Loca-
tions 13 and 14 are shared with the timer/counters to
be described later; therefore, when the timer/counters
are not used, the stack area of up to 15 levels is avail-
able. Address 7F
contents of the SPW cannot be set “15” in any case.
The SPW is automatically updated when a subroutine
call is executed or an interrupt is accepted. However, if
it is used in excess of the stack area permitted by the
data memory allocating configuration, the user-pro-
cessed data may be lost.(For example, when the user-
processed data area is in an address range 00
through 4F
H
H
, up to location 4 of the stacks are
(3F
H
through 7B
H
H
for the 47C101) in the data memory
is assigned to the SPW, so that the
H
). Each location consists
H
(3)
usable.If an interrupt is accepted with location 4
already used, the user-processed data stored in
addresses 4C
location 3 area is lost.)
The SPW is not initialized by hardware, requiring to
write the initial value (the location with which the use of
the stack starts) by using the initialization routine. Nor-
mally, the initial value of “12” is used.
Example:
Data Counter (DC)
The data counter is a 12-bit register to specify the
address of the data table to be referenced in the pro-
gram memory (ROM). Data table reference is per-
formed by the table look-up instructions [LDL A, @DC]
and [LDH A, @DC +]. The data table may be located
anywhere within the program memory address space.
The DC is assigned with a RAM address in unit of 4
bits. Therefore, the RAM manipulation instruction is
used to set the initial value or read the contents of the
DC.
Example:
LD
ST
LD
ST
ST
ST
Figure 2-7. Data Counter
To initialize the SPW (when the stack is
used from location 12)
To set the DC to 380
A,#12 ;
A,0FFH
HL,#07CH
#0H,@HL+ ; DC 380H
#8H,@HL+
#3H,@HL+
H
through 4F
TOSHIBA CORPORATION
H
SPW 12
; Sets RAM address of
corresponding to the
DC
L
H.
to HL register pair.