TMP47C990E TOSHIBA [Toshiba Semiconductor], TMP47C990E Datasheet - Page 22

• Manufacturer Part Number: TMP47C990E
• Description: CMOS 4-bit Microcontroller
• Manufacturer: TOSHIBA [Toshiba Semiconductor]

TMP47C101/201
22/32
(1)
(2)
Ports R4 (R43 to R40), R5 (R53 to 50)
These ports are 4-bit I/O ports with a latch. When used
as an input port, the latch must be set to “1”. The latch
is initialized to “1” during reset. Port R4 can directly
drive LEDs.
These 2 ports (8 pins) can be set, cleared, and tested
for each bit as specified by L register indirect address-
ing bit manipulation instructions ([SET @L], [CLR @L],
Port R8 (R81 to R80) and Port KE
Port R8 is a 2-bit I/O port with a latch.When used as
an input port, the latch must be set to “1”. The latch is
initialized to “1” during reset.
Port R8 is shared with the external interrupt input pin
and the timer/counter input pin. To use this port for
one of these functional pins, the latch should be set to
“1”. To us it for an ordinary I/O port, the acceptance of
external interrupt should be disabled or the event
counter/pulse width measurement modes of the timer/
counter should be disabled.
R82, R83 pins do not exist actually but R82, R83 has
the latch. And R82 is wired to HOLD (INT1) pin, inter-
nally.
Table 3-2. Relationship Between L Register Contents and I/O Port Bits.
Figure 3-3. Ports R4, R5
Note:
Example:
and [TEST @L]). Table 3-1 lists the pins (I/O ports) that
correspond to the contents of L register.
Port KE (KEO) is a 1-bit sense input port shared with
the hold request/release signal input in (HOLD). This
input port is assigned to the least significant bit of port
address IPOE and is processed as the data with
inverted polarity. For example, if an input instruction is
executed with the pin on the high level, ”0” is read. The
bit1 to bit3 of port KE, and undefined value is read
when an input instruction is executed.
When HOLD (INT1) pin is used for an I/O port, external interrupt 1
occurs upon detection of the falling edge of pin input, and if the
interrupt enable master flip-flop is enabled, the interrupt request is
always accepted. So that a dummy interrupt processing must be
performed (only the interrupt return instruction [RETI] is executed).
With R80 (INT2) pin, external interrupt 2 occurs like HOLD (INT1)
in but bit 0 of the interrupt enable register (EIR
“0”not accepting the interrupt request.
LD
CLR @L
To clear R43 output as specified by the L
register indirect addressing bit manipulation
instruction.
L, #00011B
TOSHIBA CORPORATION
; Sets R43 pin address to L
; R43 0
register
0
) is only kept at