NJM4558ISO8X CADEKA [Cadeka Microcircuits LLC.], NJM4558ISO8X Datasheet - Page 10

• Manufacturer Part Number: NJM4558ISO8X
• Description: Dual 4V to 36V Amplifier
• Manufacturer: CADEKA [Cadeka Microcircuits LLC.]

Data Sheet
can be calculated as above with the desired signal ampli-
tudes using:
(V
( I
The dynamic power is focused primarily within the output
stage driving the load. This value can be calculated as:
P
Assuming the load is referenced in the middle of the pow-
er rails or V
Figure 4 shows the maximum safe power dissipation in
the package vs. the ambient temperature for the pack-
ages available.
Driving Capacitive Loads
Increased phase delay at the output due to capacitive
loading can cause ringing, peaking in the frequency re-
sponse, and possible unstable behavior. Use a series re-
sistance, R
improve stability and settling performance. Refer to Fig-
ure 5.
©2008-2010 CADEKA Microcircuits LLC
DYNAMIC
Input
LOAD
LOAD
1.5
0.5
2
1
0
-40
)
)
RMS
RMS
R
= (V
g
S
Figure 4. Maximum Power Derating
Figure 5. Addition of R
supply
= V
= ( V
, between the amplifier and the load to help
+
-
-20
S+
PEAK
R
/2.
LOAD
- V
f
/ √2
LOAD
Capacitive Loads
Ambient Temperature (°C)
0
)
RMS
R
)
RMS
s
/ Rload
SOIC-8
20
× ( I
C
L
eff
S
LOAD
40
for Driving
R
L
)
RMS
Output
60
80
Overdrive Recovery
An overdrive condition is defined as the point when ei-
ther one of the inputs or the output exceed their specified
voltage range. Overdrive recovery is the time needed for
the amplifier to return to its normal or linear operating
point. The recovery time varies, based on whether the
input or output is overdriven and by how much the range
is exceeded. The NJM4558 will typically recover in less
than 30ns from an overdrive condition. Figure 6 shows the
NJM4558 in an overdriven condition.
Layout Considerations
General layout and supply bypassing play major roles
in high frequency performance. CADEKA has evaluation
boards to use as a guide for high frequency layout and as
an aid in device testing and characterization. Follow the
steps below as a basis for high frequency layout:
• Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
• Place the 6.8µF capacitor within 0.75 inches of the power pin
• Place the 0.1µF capacitor within 0.1 inches of the power pin
• Remove the ground plane under and around the part,
especially near the input and output pins to reduce para-
sitic capacitance
• Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts below for more in-
formation.
-10
10
-5
5
0
0
Input
10
Figure 6. Overdrive Recovery
20
Output
Time (us)
30
40
V
G = 5
IN
www.cadeka.com
= 7.5V
pp
50
20
10
0
-10
-20
10