HIP6601A INTERSIL [Intersil Corporation], HIP6601A Datasheet - Page 7

• Manufacturer Part Number: HIP6601A
• Description: Synchronous Rectified Buck MOSFET Drivers
• Manufacturer: INTERSIL [Intersil Corporation]

be performed to ensure safe operation at the desired
frequency for the selected MOSFETs. The power dissipated
by the driver is approximated as:
where f
and V
and Q
MOSFET selection and any external capacitance added to
the gate pins. The I
of the driver and is typically 30mW.
The power dissipation approximation is a result of power
transferred to and from the upper and lower gates. But, the
internal bootstrap device also dissipates power on-chip
during the refresh cycle. Expressing this power in terms of
the upper MOSFET total gate charge is explained below.
The bootstrap device conducts when the lower MOSFET or
its body diode conducts and pulls the PHASE node toward
GND. While the bootstrap device conducts, a current path is
formed that refreshes the bootstrap capacitor. Since the
upper gate is driving a MOSFET, the charge removed from
the bootstrap capacitor is equivalent to the total gate charge
of the MOSFET. Therefore, the refresh power required by
the bootstrap capacitor is equivalent to the power used to
charge the gate capacitance of the MOSFET.
where Q
capacitor and provided to the upper gate load.
The 1.05 factor is a correction factor derived from the
following characterization. The base circuit for characterizing
the drivers for different loading profiles and frequencies is
provided. C
capacitors. Decoupling capacitors [0.15µF] are added to the
PVCC and VCC pins. The bootstrap capacitor value is
0.01µF.
In Figure 1, C
is varied from 50kHz to 2MHz. PVCC and VCC are tied
together to a +12V supply. Curves do exceed the 800mW
cutoff, but continuous operation above this point is not
recommended.
Figure 2 shows the dissipation in the driver with 3nF loading
on both gates and each individually. Note the higher upper
gate power dissipation which is due to the bootstrap device
refresh cycle. Again PVCC and VCC are tied together and to
a +12V supply.
P
P
REFRESH
=
1.05f
L
L
sw
represent the upper and lower gate rail voltage. Q
is the upper and lower gate charge determined by
LOSS
sw
is the switching frequency of the PWM signal. V
U


=
3
-- - V
2
and C
U
1
-- - f
2
is the total charge removed from the bootstrap
U
and C
SW
Q
U
DDQ
Q
L
+
LOSS
are the upper and lower gate load
V
L
L
values are the same and frequency
V
Q
CC
L
V


PVCC
+
product is the quiescent power
7
I
DDQ
=
V
1
-- - f
2
CC
SW
Q
U
HIP6601A, HIP6603A, HIP6604
V
U
U
U
Test Circuit
The impact of loading on power dissipation is shown in
Figure 3. Frequency is held constant while the gate
capacitors are varied from 1nF to 5nF. VCC and PVCC are
tied together and to a +12V supply. Figures 4 through 6
show the same characterization for the HIP6603A with a
+5V supply on PVCC and VCC tied to a +12V supply.
+12V
1000
800
600
400
200
1000
800
600
400
200
FIGURE 1. POWER DISSIPATION vs FREQUENCY
0.15µF
0.15µF
+5V OR +12V
0
0
VCC = PVCC = 12V
C
U
FIGURE 2. 3nF LOADING PROFILE
= C
C
U
PVCC
PWM
L
VCC
= C
+5V OR +12V
= 3nF
500
500
L
= 3nF
C
C
U
U
FREQUENCY (kHz)
FREQUENCY (kHz)
= C
= C
BOOT
GND
L
L
0.01µF
= 4nF
= 5nF
UGATE
PHASE
LGATE
1000
1000
C
C
C
U
L
2N7002
L
= 0nF
= 3nF
VCC = PVCC = 12V
C
C
C
U
L
U
= 0nF
= 3nF
= C
C
1500
1500
U
2N7002
L
= C
= 1nF
L
100kΩ
= 2nF
C
2000
2000
U