HIP6500BEVAL1 INTERSIL [Intersil Corporation], HIP6500BEVAL1 Datasheet

HIP6500BEVAL1

Manufacturer Part Number

HIP6500BEVAL1

Description

Multiple Linear Power Controller with ACPI Control Interface

Manufacturer

INTERSIL [Intersil Corporation]

Datasheet

1.HIP6500BEVAL1.pdf (15 pages)

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Multiple Linear Power Controller with

ACPI Control Interface

The HIP6500B complements either an HIP6020 or an HIP6021

in ACPI-compliant designs for microprocessor and computer

applications. The IC integrates two linear controllers and two

regulators, switching, monitoring and control functions into a

20-pin SOIC package. One linear controller generates the

3.3V

powering the PCI slots through an external pass transistor

during sleep states (S3, S4/S5). A second transistor is used to

switch in the ATX 3.3V output for operation during S0 and

S1/S2 (active) operating states. The second linear controller

supplies the computer system’s 2.5V/3.3V memory power

through an external pass transistor in active states. During S3

state, an integrated pass transistor supplies the 2.5V/3.3V

sleep power. A third controller powers up the 5V

switching in the ATX 5V output in active states, and the ATX

5VSB in sleep states. The two internal regulators consist of a

low current 3.3V sleep output and a dedicated, noise-free 2.5V

clock chip supply. The HIP6500B’s operating mode (active

outputs or sleep outputs) is selectable through two digital

control pins, S3 and S5. Further control of the logic governing

activation of different power states is offered through two

configuration pins, EN3VDL and EN5VDL. In active state, the

3.3V

MOSFET to connect the output directly to the 3.3V input

supplied by an ATX (or equivalent) power supply, for minimal

losses. In sleep state, power delivery on the 3.3V

transferred to an NPN transistor, also external to the controller.

Active state power delivery for the 2.5/3.3V

performed through an external NPN transistor, or an NMOS

switch for the 3.3V setting. In sleep state, conduction on this

output is transferred to an internal pass transistor. The 5V

output is powered through two external MOS transistors. In

sleep states, a PMOS (or PNP) transistor conducts the current

from the ATX 5VSB output; while in active state, current flow is

transferred to an NMOS transistor connected to the ATX 5V

output. Similar to the 3.3V

S5 pins, but that of the EN5VDL pin as well. The 3.3V

internal regulator is active for as long as the ATX 5VSB voltage

is applied to the chip, and derives its output current from the

5VSB pin. The 2.5V

and uses the 3V3 pin as input source for its internal pass

element.

Ordering Information

HIP6500BCB

HIP6500BEVAL1

PART NUMBER

DUAL

output is dictated not only by the status of the S3 and

voltage plane from the ATX supply’s 5VSB output,

linear regulator uses an external N-Channel pass

CLK

Evaluation Board

RANGE (

TEMP.

0 to 70

output is only active during S0 and S1,

DUAL

output, the operation of the

20 Ld SOIC

1-888-INTERSIL or 321-724-7143

Data Sheet

PACKAGE

MEM

DUAL

output is

DUAL

M20.3

plane by

output is

PKG.

NO.

DUAL

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil and Design is a trademark of Intersil Corporation.

Features

• Provides 5 ACPI-Controlled Voltages

• Excellent Output Voltage Regulation

• Small Size

• Selectable Memory Output Voltage Via FAULT/MSEL Pin

• Under-Voltage Monitoring of All Outputs with Centralized

Applications

• Motherboard Power Regulation for ACPI-Compliant

Pinout

- 5V Active/Sleep (5V

- 3.3V Active/Sleep (3.3V

- 2.5V/3.3V Active/Sleep (2.5/3.3V

- 3.3V Always Present (3.3V

- 2.5V Clock (Active Only) (2.5V

- 3.3V

- 2.5V/3.3V

- 2.5V

- Very Low External Component Count

- 2.5V for RDRAM Memory

- 3.3V for SDRAM Memory

FAULT Reporting and Temperature Shutdown

Computers

Only

Operational States (3.3V setting in sleep only)

DUAL

CLK

3V3DLSB

EN5VDL

and 3.3V

VSEN2

3V3SB

3V3DL

May 2000

MEM

VCLK

Output: 2% Over Temperature; Sleep State

5VSB

3V3

Output: 2% Over Temperature; Both

DUAL

TOP VIEW

HIP6500B

Output: 2% Over Temperature

(SOIC)

DUAL

)

File Number

CLK

MEM

)

EN3VDL

5VDL

5VDLSB

DLA

FAULT/MSEL

HIP6500B

DRV2

12V

GND

)

Intersil Corporation 2000

4870

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HIP6500BEVAL1 Summary of contents

Page 1

... Ordering Information TEMP. o PART NUMBER RANGE ( C) PACKAGE HIP6500BCB SOIC HIP6500BEVAL1 Evaluation Board 1 1-888-INTERSIL or 321-724-7143 Features • Provides 5 ACPI-Controlled Voltages - 5V Active/Sleep (5V - 3.3V Active/Sleep (3.3V - 2.5V/3.3V Active/Sleep (2.5/3.3V - 3.3V Always Present (3.3V - 2.5V Clock (Active Only) (2.5V • Excellent Output Voltage Regulation - 3 ...

Page 2

Block Diagram 12V 12V MONITOR 10.8V/9.8V TO 5VSB EA3 + - TO UV 3V3SB DETECTOR FAULT/MSEL UV DETECTOR TO 5VSB COMPARATOR 3.75V - 5VDL GND 3V3DL 5V 3V3 3V3DLSB 5VSB EA4 - + 3V3 ...

Page 3

Simpliﬁed Power System Diagram +5V IN +12V IN +5V SB +3. 3.3V DUAL 3.3V FAULT/MSEL SHUTDOWN SX 2 ENXVDL 2 Typical Application +5V IN +12V IN +5V SB +3. OUT1 3. OUT1 ...

Page 4

Absolute Maximum Ratings Supply Voltage +7.0V 5VSB 12V. . ...

Page 5

Electrical Speciﬁcations Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3 (Continued) PARAMETER DRV2 Output Drive Current DRV2 Output Impedance 3.3V LINEAR REGULATOR (V DUAL OUT3 Sleep State Regulation 3V3DL Nominal Voltage Level 3V3DL Undervoltage Rising ...

Page 6

Functional Pin Descriptions 3V3 (Pin 7) Connect this pin to the ATX 3.3V output. This pin provides the output current for the 2V5CLK pin, and is monitored for power quality. 5VSB (Pin 2) Provide a very well de-coupled 5V bias ...

Page 7

This pin is the output of the internal 3. This internal regulator operates continuously for as OUT1 long as the 5VSB bias voltage is applied to the HIP6500B. This pin is monitored for under-voltage events. ...

Page 8

Functional Timing Diagrams Figures 4 through 8 are timing diagrams, detailing the power up/down sequences of all three outputs in response to the status of the enable (EN3VDL, EN5VDL) and sleep-state pins (S3, S5), as well as the status of ...

Page 9

S3 S5 12V INTERNAL VSEN2 DEVICE DRV2 VSEN2 3V3SB VCLK FIGURE 8. 2.5/3.3V , 3.3V AND VCLK TIMING DIAGRAM MEM SB Soft-Start Circuit SOFT-START INTO SLEEP STATES (S3, S4/S5) The 5VSB POR function initiates the soft-start sequence. An internal ...

Page 10

SOFT-START INTO ACTIVE STATES (S0, S1) If both S3 and S5 are logic high at the time the 5VSB is applied, the HIP6500B will assume active state wake-up and keep off the controlled external transistors and the VCLK output until ...

Page 11

FAULT/MSEL pin and ground. An internal 40 A (typical) current source creates a voltage drop across this resistor. Following every 3.3V ramp-up or chip reset (see SB Soft-Start ...

Page 12

Placement of the decoupling and bulk capacitors should follow a placement reﬂecting their purpose. As such, the high-frequency decoupling capacitors should be placed as close as possible to the load they are decoupling; the ones decoupling the controller close to ...

Page 13

Transistor Selection/Considerations The HIP6500B usually requires one P-Channel (or bipolar PNP), two N-Channel MOSFETs and two bipolar NPN transistors. One important criteria for selection of transistors for all the linear regulators/switching elements is package selection for efﬁcient removal of heat. ...

Page 14

HIP6500B Application Circuit Figure 14 shows an application circuit of an ACPI- sanctioned power management system for a microprocessor computer system. The power supply provides the 3.3V voltage (V ), the PCI 3.3V voltage (V OUT1 DUAL RDRAM 2.5VMEM memory ...

Page 15

Small Outline Plastic Packages (SOIC) N INDEX H AREA SEATING PLANE 0.10(0.004) 0.25(0.010) M NOTES: 1. Dimension “D” does not include mold flash, protrusions or gate burrs. 2. Dimension “E” does ...

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