hip6500 Intersil Corporation, hip6500 Datasheet
hip6500
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hip6500 Summary of contents
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... Data Sheet Multiple Linear Power Controller with ACPI Control Interface The HIP6500 complements either an HIP6020 or an HIP6021 in ACPI-compliant designs for microprocessor and computer applications. The IC integrates two linear controllers and two regulators, switching, monitoring and control functions into a 20-pin SOIC package. One linear controller generates the 3.3V voltage plane from the ATX supply’ ...
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Block Diagram 12V 12V MONITOR 10.2V/9.2V TO 5VSB EA3 + - TO UV 3V3SB DETECTOR FAULT/MSEL UV DETECTOR TO 5VSB COMPARATOR 3.75V - 5VDL GND 3V3DL 5V 3V3 3V3DLSB 5VSB 5VSB POR EA4 - ...
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... OUT3 3.3V DUAL C OUT3 FAULT SLP_S3 SLP_S5 EN5VDL EN3VDL SHUTDOWN 3 HIP6500 SB LINEAR REGULATOR 3.3V LINEAR CONTROLLER HIP6500 FIGURE 2. 12V 3V3 3V3SB 5V 3V3DLSB 3V3DL FAULT/MSEL HIP6500 R SEL S3 S5 EN5VDL EN3VDL GND FIGURE 3. Q1 LINEAR V MEM CONTROLLER 2.5V/3.3V V LINEAR CLK REGULATOR 2.5V CONTROL LOGIC 5VSB Q1 DRV2 ...
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... VSEN2 Nominal Voltage Level VSEN2 Undervoltage Rising Threshold VSEN2 Undervoltage Hysteresis (Note 2) VSEN2 Output Current DRV2 Output Drive Current DRV2 Output Impedance 4 HIP6500 Thermal Information Thermal Resistance (Typical, Note 1) SOIC Package +0.3V 12V Maximum Junction Temperature (Plastic Package .150 Maximum Storage Temperature Range . . . . . . . . . . -65 Maximum Lead Temperature (Soldering 10s) ...
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... Low Level Input Threshold S3, S5 Internal Pull-Up Impedance to 5VSB FAULT Output Impedance TEMPERATURE MONITOR Fault-Level Threshold (Note 5) Shutdown-Level Threshold (Note 5) NOTES: 2. Valid for 3.3V setting only ambient temperatures less than 50 4. Guaranteed by correlation. 5. Guaranteed by design. 5 HIP6500 SYMBOL TEST CONDITIONS ) V 3V3DL I 5VSB = 5V 3V3DLSB ) V VCLK ...
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... ATX outputs case of an overtemperature event, this pin is used to report the fault condition by being pulled to 5VSB. 6 HIP6500 SS (Pin 16) Connect this pin to a small ceramic capacitor (no less than 5nF; 0.1 F recommended). The internal soft-start (SS) current source along with the external capacitor creates a voltage ramp used to control the ramp-up of the output voltages ...
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... This pin is the output of the internal 3. This internal regulator operates continuously for as OUT1 long as the 5VSB bias voltage is applied to the HIP6500. This pin is monitored for under-voltage events. VCLK (Pin 6) This pin is the output of the internal 2.5V clock chip regulator (V ). This internal regulator operates only in active ...
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... Additionally, the S3 pin features a 200 s delay in transitioning to sleep states. Once the S3 pin goes low, an internal timer is activated. At the end of the 200 s interval, if the S5 pin is low, the HIP6500 switches into S5 sleep state; if the S5 pin is high, the HIP6500 goes into S3 sleep state. 5VSB ...
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... TIME FIGURE 9. SOFT-START INTERVAL IN A SLEEP STATE (ALL OUTPUTS ENABLED) 9 HIP6500 Figure 9 shows the soft-start sequence for the typical application start-up in sleep state with all output voltages enabled. At time T0 5VSB (bias) is applied to the circuit. At time T1 the 5VSB surpasses POR level. An internal fast ...
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... SOFT-START INTO ACTIVE STATES (S0, S1) If both S3 and S5 are logic high at the time the 5VSB is applied, the HIP6500 will assume active state wake-up and keep off the controlled external transistors and the VCLK output until some time (typically 25ms) after the ATX’s main outputs used by the application (3 ...
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... The built-in soft-start circuitry allows tight control of the slew- up speed of the output voltages controlled by the HIP6500, thus enabling power-ups free of supply drop-off events. Since the outputs are ramped linear fashion, the ...
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... If the ATX supply does not meet the specifications, certain imbalances between the ATX’s outputs and the HIP6500’s regulation levels could have as a result a brisk transfer of energy from the input capacitors to t ...
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... At the transition between active and sleep states, this phenomena could result in the 5VSB voltage dropping below the POR level (typically 4.1V) and temporarily disabling the HIP6500. The solution to a potential problem such as this is using larger input capacitors with a lower total combined ESR. ...
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... 12V 5VSB 3V3 3V3SB 5V 3V3DLSB 3V3DL C10 U1 220 F HIP6500 FAULT/MSEL R1 1K EN5VDL EN3VDL C13 GND 0.1 F FIGURE 14. TYPICAL HIP6500 APPLICATION DIAGRAM + C2 220 DRV2 Q1 2SD1802 VSEN2 + C6,7 C8 2X150 VCLK C11 + C12 150 5VDLSB FDV304P DLA Q5 ...
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... For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 15 HIP6500 M20.3 (JEDEC MS-013-AC ISSUE C) 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE SYMBOL A ...