HIP4086AABZ INTERSIL [Intersil Corporation], HIP4086AABZ Datasheet - Page 3

• Manufacturer Part Number: HIP4086AABZ
• Description: 80V, 500mA, 3-Phase MOSFET Driver 1.25A peak turn-off current
• Manufacturer: INTERSIL [Intersil Corporation]

Pin Configuration
Pin Descriptions
PIN NUMBER
16
13
15
23
15
12
11
10
1
5
2
4
3
6
7
8
9
3
SYMBOL
RFSH
(xHB)
(xHS)
RDEL
UVLO
(xHI)
AHB
BHB
CHB
AHS
BHS
CHS
(xLI)
AHI
BHI
CHI
V
DIS
ALI
BLI
CLI
SS
HIP4086, HIP4086A
High-Side Bias Connections. One external bootstrap diode and one capacitor are required for
each. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to each xHB
pin.
High-Side Source Connections. Connect the sources of the High-Side power MOSFETs to these
pins. The negative side of the bootstrap capacitors are also connected to these pins.
High-Side Logic Level Inputs. Logic at these three pins controls the three high side output
drivers, AHO (Pin 17), BHO (Pin 24) and CHO (Pin 14). When xHI is low, xHO is high. When xHI
is high, xHO is low. Unless the dead time is disabled by connecting RDEL (Pin 7) to ground, the
low side input of each phase will override the corresponding high side input on that phase -
see “Truth Table” on page 2. If RDEL is tied to ground, dead time is disabled and the outputs
follow the inputs with no shoot-thru protection. DIS (Pin 10) also overrides the high side inputs.
xHI can be driven by signal levels of 0V to 15V (no greater than V
Low-Side Logic Level Inputs. Logic at these three pins controls the three low-side output
drivers ALO (Pin 21), BLO (Pin 22) and CLO (Pin 19). If the upper inputs are grounded then the
lower inputs control both xLO and xHO drivers, with the dead time set by the resistor at RDEL
(Pin 7). DIS (Pin 10) high level input overrides xLI, forcing all outputs low. xLI can be driven by
signal levels of 0V to 15V (no greater than V
Ground. Connect the sources of the Low-Side power MOSFETs to this pin.
Delay Time Set point. Connect a resistor from this pin to V
the dead time between drivers - see Figure 17. All drivers turn-off with minimal delay, RDEL
resistor prevents shoot-through by delaying the turn-on of all drivers. When RDEL is tied to V
both upper and lowers can be commanded on simultaneously. While not necessary in most
applications, a decoupling capacitor of 0.1µF or smaller may be connected between RDEL and
V
Under voltage Set point. A resistor can be connected between this pin and V
under voltage set point, see Figure 18. With this pin not connected, the under voltage disable
is typically 6.6V. When this pin is tied to V
Refresh Pulse Setting. An external capacitor can be connected from this pin to V
the length of the start up refresh pulse - see Figure 16. If this pin is not connected, the refresh
pulse is typically 1.5µs.
Disable Input. Logic level input that when taken high sets all six outputs low. DIS high
overrides all other inputs. With DIS low, the outputs are controlled by the other inputs. DIS can
be driven by signal levels of 0V to 15V (no greater than V
SS
.
UVLO
RDEL
RFSH
BHB
VSS
BHI
AHI
CHI
BLI
ALI
DIS
CLI
HIP4086, HIP4086A
10
11
12
1
2
3
4
5
6
7
8
9
(PDIP, SOIC)
TOP VIEW
24
23
22
21
20
19
18
17
16
15
14
13
BHO
BHS
BLO
ALO
VDD
CLO
AHS
AHC
AHB
CHS
CHO
CHB
DESCRIPTION
DD
DD
, the under voltage disable is typically 6.2V.
).
DD
DD
).
to set timing current that defines
DD
).
SS
to program the
SS
to increase
June 1, 2011
FN4220.7
SS
,