STM8L151K6U3 STMICROELECTRONICS [STMicroelectronics], STM8L151K6U3 Datasheet - Page 53

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STM8L151K6U3

Manufacturer Part Number
STM8L151K6U3
Description
8-bit ultralow power MCU, up to 32 KB Flash, 1 KB Data EEPROM RTC, LCD, timers, USART, I2C, SPI, ADC, DAC, comparators
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet

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0
STM8L151xx, STM8L152xx
Table 11.
Option
OPT0
OPT1
OPT2
OPT3
OPT4
byte
No.
ROP[7:0] Memory readout protection (ROP)
UBC[7:0] Size of the user boot code area
PCODESIZE[7:0] Size of the proprietary code area
Refer to
details.
IWDG_HW: Independent watchdog
IWDG_HALT: Independent window watchdog reset on Halt/Active-halt
WWDG_HW: Window watchdog
WWDG_HALT: Window window watchdog reset on Halt/Active-halt
HSECNT: Number of HSE oscillator stabilization clock cycles
LSECNT: Number of LSE oscillator stabilization clock cycles
Option byte description
0xAA: Enable Readout protection (write access via SWIM protocol)
Refer to Readout protection section in the STM8L15x reference manual (RM0031).
0x00: no UBC
0x01: the UBC contains only the interrupt vectors.
0x02: Page 0 and 1 reserved for the UBC and read/write protected. Page 0 contains only the interrupt
vectors.
0x03 - Page 0 to 3 reserved for UBC, memory write-protected
≥ 0xFF - Page 0 to 255 reserved for UBC, memory write-protected
Refer to User boot code section in the STM8L15x reference manual (RM0031).
0x00: no proprietary code area
0x02: Page 0 and 1 reserved for the proprietary code and read/write protected. Page 0 contains only
the interrupt vectors.
≥ 0xFF - Page 0 o 254 reserved for the proprietary code. Only page 1 to 254 are read/write protected.
Page 255 is always left free.
0: Independent watchdog activated by software
1: Independent watchdog activated by hardware
0: Independent watchdog continues running in Halt/Active-halt mode
1: Independent watchdog stopped in Halt/Active-halt mode
0: Window watchdog activated by software
1: Window watchdog activated by hardware
0: Window watchdog stopped in Halt mode
1: Window watchdog generates a reset when MCU enters Halt mode
0x00 - 1 clock cycle
0x01 - 16 clock cycles
0x10 - 512 clock cycles
0x11 - 4096 clock cycles
0x00 - 1 clock cycle
0x01 - 16 clock cycles
0x10 - 512 clock cycles
0x11 - 4096 clock cycles
Proprietary code area (PCODE)
Doc ID 15962 Rev 2
Option description
section in the STM8L reference manual (RM0013) for more
Option bytes
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