NCP5106A ONSEMI [ON Semiconductor], NCP5106A Datasheet

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NCP5106A

Manufacturer Part Number
NCP5106A
Description
High Voltage, High and Low Side Driver
Manufacturer
ONSEMI [ON Semiconductor]
Datasheet

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NCP5106A, NCP5106B
High Voltage, High and Low
Side Driver
outputs for direct drive of 2 N−channel power MOSFETs or IGBTs
arranged in a half−bridge configuration version B or any other
high−side + low−side configuration version A.
high−side power switch. The driver works with 2 independent inputs.
Features
Typical Applications
© Semiconductor Components Industries, LLC, 2010
March, 2010 − Rev. 5
The NCP5106 is a high voltage gate driver IC providing two
It uses the bootstrap technique to ensure a proper drive of the
for Signal Propagation
(Version B)
Active Clamp) (A Version Only).
High Voltage Range: Up to 600 V
dV/dt Immunity ±50 V/nsec
Negative Current Injection Characterized Over the Temperature Range
Gate Drive Supply Range from 10 V to 20 V
High and Low Drive Outputs
Output Source / Sink Current Capability 250 mA / 500 mA
3.3 V and 5 V Input Logic Compatible
Up to V
Extended Allowable Negative Bridge Pin Voltage Swing to −10 V
Matched Propagation Delays Between Both Channels
Outputs in Phase with the Inputs
Independent Logic Inputs to Accommodate All Topologies (Version A)
Cross Conduction Protection with 100 ns Internal Fixed Dead Time
Under V
Pin−to−Pin Compatible with Industry Standards
These are Pb−Free Devices
Half−Bridge Power Converters
Any Complementary Drive Converters (Asymmetrical Half−Bridge,
Full−Bridge Converters
CC
CC
Swing on Input Pins
LockOut (UVLO) for Both Channels
1
†For information on tape and reel specifications,
NCP5106APG
NCP5106ADR2G
NCP5106BPG
NCP5106BDR2G
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Device
NCP5106 = Specific Device Code
x
A
L or WL
Y or YY
W or WW = Work Week
G or G
CASE 751
CASE 626
ORDERING INFORMATION
D SUFFIX
P SUFFIX
SOIC−8
IN_LO
PDIP−8
1
IN_HI
GND
VCC
PINOUT INFORMATION
http://onsemi.com
1
8 Pin Package
= A or B version
= Assembly Location
= Wafer Lot
= Year
= Pb−Free Package
(Pb−Free)
(Pb−Free)
(Pb−Free)
(Pb−Free)
Package
SOIC−8
SOIC−8
PDIP−8
PDIP−8
1
2
3
4
Publication Order Number:
8
7
6
5
DIAGRAMS
8
1
MARKING
2500 / Tape & Reel
2500 / Tape & Reel
VBOOT
DRV_HI
BRIDGE
DRV_LO
NCP5106x
50 Units / Rail
50 Units / Rail
ALYW
5106x
Shipping
G
YYWW
NCP5106/D
AWLG

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NCP5106A Summary of contents

Page 1

... NCP5106A, NCP5106B High Voltage, High and Low Side Driver The NCP5106 is a high voltage gate driver IC providing two outputs for direct drive of 2 N−channel power MOSFETs or IGBTs arranged in a half−bridge configuration version B or any other high−side + low−side configuration version A. ...

Page 2

Vbulk C1 D4 GND Vcc GND VBOOT Vcc 2 IN_HI DRV_HI NCP1395 3 IN_LO 4 GND DRV_LO NCP5106 GND GND Figure 1. Typical Application Resonant Converter (LLC type) + Vbulk C1 D4 GND Vcc C3 U1 ...

Page 3

VCC VCC UV DETECT IN_HI GND IN_LO DELAY GND GND GND Figure 3. Detailed Block Diagram: Version A VCC VCC UV DETECT IN_HI CROSS GND CONDUCTION PREVENTION IN_LO GND Figure 4. Detailed Block Diagram: Version B PIN DESCRIPTION Pin Name ...

Page 4

MAXIMUM RATINGS Rating V Main power supply voltage CC V Main transient power supply voltage: CC_transient during 10 ms CC_max V VHV: High Voltage BRIDGE pin BRIDGE V Allowable Negative Bridge Pin Voltage for IN_LO Signal ...

Page 5

ELECTRICAL CHARACTERISTIC (V Rating OUTPUT SECTION Output high short circuit pulsed current V DRV Output low short circuit pulsed current V DRV Output resistor (Typical value @ 25°C) Source Output resistor (Typical value @ 25°C) Sink High level output voltage, ...

Page 6

IN_HI IN_LO DRV_HI DRV_LO Figure 5. Input/Output Timing Diagram (A Version) IN_HI IN_LO DRV_HI DRV_LO Figure 6. Input/Output Timing Diagram (B Version) 50% IN_HI (IN_LO DRV_HI (DRV_LO) 10% Figure 7. Propagation Delay and Rise / Fall ...

Page 7

IN_LO & 50% IN_HI ton_HI Delta_t DRV_HI ton_LO DRV_LO 10% Figure 8. Matching Propagation Delay (A Version) 50% IN_HI ton_HI DRV_HI 50% IN_LO toff_LO 90% DRV_LO Figure 9. Matching Propagation Delay (B Version) 50% toff_HI 90% 10% toff_LO Matching Delay ...

Page 8

IN_HI IN_LO DRV_HI DRV_LO Internal Deadtime Figure 10. Input/Output Cross Conduction Output Protection Timing Diagram (B Version) http://onsemi.com 8 Internal Deadtime ...

Page 9

T High Side ON 100 Low Side VOLTAGE (V) CC Figure 11. Turn ON Propagation Delay vs. Supply Voltage ( 140 120 ...

Page 10

Low Side VOLTAGE (V) CC Figure 17. Turn ON Risetime vs. Supply Voltage ( BOOT Low ...

Page 11

V , VOLTAGE (V) CC Figure 23. Low Level Input Voltage Threshold vs. Supply Voltage (V 2.5 2 1 ...

Page 12

V , VOLTAGE (V) CC Figure 29. Logic “1” Input Current vs. Supply Voltage ( BOOT 1 0.8 0.6 0.4 0 ...

Page 13

I High Side src 300 250 I src 200 150 100 VOLTAGE (V) CC Figure 35. Output Source Current vs. Supply Voltage ( BOOT 600 I High ...

Page 14

V , VOLTAGE (V) BOOT Figure 41. V Supply Current vs. Bootstrap BOOT Supply Voltage 240 200 160 120 VOLTAGE (V) ...

Page 15

... Frequency with 50 nC Load on Each Driver @ −5 −10 −15 −20 −25 −30 −35 0 100 200 300 400 NEGATIVE PULSE DURATION (ns) Figure 51. NCP5106A, Negative Voltage Safe Operating Area on the Bridge Pin CHARACTERIZATION CURVES 40 C LOAD 100 500 600 Figure 48 ...

Page 16

... By this way the negative voltage applied to the bridge pin will be limited by D1 and R1 and will prevent any wrong behavior. http://onsemi.com 16 D2 Vbulk MUR160 U1 C1 NCP5106A 100n 1 8 VCC VBOOT 2 7 IN_HI DRV_HI ...

Page 17

0.25 (0.010 −Y− SEATING PLANE −Z− 0.25 (0.010 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor ...

Page 18

F −A− NOTE 2 −T− N SEATING PLANE 0.13 (0.005) The product described herein is covered by U.S. patents: 6,097,075; 7,176,723; 6,362,067. There may be some other patents pending. ON Semiconductor and are ...

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