ADP3178JR AD [Analog Devices], ADP3178JR Datasheet - Page 11

• Manufacturer Part Number: ADP3178JR
• Description: 4-Bit Programmable Synchronous Buck Controllers
• Manufacturer: AD [Analog Devices]

To correctly implement active voltage positioning, the low fre-
quency output impedance (i.e., the output resistance) of the
converter should be made equal to the maximum ESR of the
output capacitor array. This can be achieved by having a single-
pole roll-off of the voltage gain of the g
the pole frequency coincides with the ESR zero of the output
capacitor. A gain with single-pole roll-off requires that the g
amplifier output pin be terminated by the parallel combination
of a resistor and capacitor. The required resistor value can be
calculated from the equation:
where:
In Equations 24 and 25, R
amplifier, n
signal of the g
transconductance of the g
Although a single termination resistor equal to R
the proper voltage positioning gain, the dc biasing of that resistor
would determine how the regulation band is centered (i.e., offset).
Note that sometimes the specified regulation band is asymmetrical
with respect to the nominal VID voltage. With the ADP3158 and
ADP3178, the offset is already considered part of the design
procedure—no special provision is required. To accomplish the dc
biasing, it is simplest to use two resistors to terminate the g
amplifier output, with the lower resistor (R
the upper resistor (R
these resistors can be calculated using:
R
A
R
R
g
m
TOTAL
COMP
100
90
80
70
60
50
40
30
20
10
(
V
0
OUT OS
V
0
I
DIV
is the division ratio from the output voltage to
m
(
R
R
g
n
2
m
amplifier to the PWM comparator, and g
OGM
OGM
)
I
K
R
A
R
4
–
) to the 12 V supply of the IC. The values of
)
E MAX
SENSE
(
R
R
2 2
TOTAL
TOTAL
6
.
m
OUTPUT CURRENT – A
OGM
)
mmho
amplifier itself.
8
2 2
is the internal resistance of the g
.
1
1
(
10
25 4
M
M
mmho
22
12
mV
V
12
m
– .
9 1
m
9 1
error amplifier, where
B
.
4 7 10
) tied to ground and
5
14
.
m
k
k
COMP
16
–
2
9 2
9 1
)
.
.
would yield
18
79 1
k
k
.
20
m
k
is the
m
m
(24)
(25)
(26)
m
where K is a constant determined by internal characteristics of the
ADP3158 and ADP3178, peak-to-peak inductor current ripple
(I
calculated using Equations 28 and 29. V
supply voltage (e.g., the recommended 12 V supply) and V
the output voltage offset from the nominal VID-programmed value
under no load condition. This offset is given by Equation 30.
The closest 1% value for R
to solve for R
The nearest 1% value of 10.5 k was chosen for R
V
V
V
V
Finally, the compensating capacitance is determined from the
equality of the pole frequency of the error amplifier gain and the
zero frequency of the impedance of the output capacitor:
The closest standard value for C
K
K
C
R
GNL
GNL
OUT OS
OUT OS
RIPPLE
OC
B
4 7 10
.
(
(
I
3 8
L RIPPLE
.
V
1
(
2
R
R
), and the current sampling resistor (R
)
)
GNL
V
C
A
2
–
A
A
2
OUT
40
–
0
V
R
3 8
2 2
)
OUT MAX
TOTAL
R
R
.
.
mV
B
I
COMP
COMP
mmho
(
L RIPPLE
A
:
4
g
(
R
(
ESR
m
m
SENSE
4
2
5
R
m
)
TOTAL
9 1
m
25
.
)
V
78 7
78 7
n
k
2
VID
I
R
5
2
25
)
SENSE
.
.
3 8
mF
.
A
k
k
g
9 1
2 2
R
A
is 78.7 k . This value is then used
m
5
.
.
ADP3158/ADP3178
V
E MAX
1 5
V
– .
mmho
(
4 8
n
.
k
GNL
R
– .
1 7
I
OC
9 2
9 2
.
TOTAL
1 174
.
1 7
.
.
H
V
m
)
is 2.7 nF.
V
V
k
k
2
9 1
IN
.
I
–
5 10
L RIPPLE
DIV
k
2
75
(
L
V
2 6
ns
10 4
VID
g R
V
is the resistor divider
.
m
2 2 2
SENSE
–
CC
3
.
)
4
nF
OGM
m
t
k
.
22
D
V
). K can be
mmho
VID
12
mV
B
R
.
25
SENSE
V
k
VID
130
OUT(OS)
1 174
.
k
(30)
n
(29)
I
(28)
(27)
(31)
V
is