NCP1611ADR2G ONSEMI [ON Semiconductor], NCP1611ADR2G Datasheet - Page 24

• Manufacturer Part Number: NCP1611ADR2G
• Description: Enhanced, High-Efficiency Power Factor Controller
• Manufacturer: ONSEMI [ON Semiconductor]

external loop compensation. Typically a type 2 network is
applied between pin1 and ground, to set the regulation
bandwidth below about 20 Hz and to provide a decent phase
boost.
The swing of the error amplifier output is limited within an
accurate range:
variations of the load, may result in excessive over or
under−shoot. Over−shoot is limited by the Over−Voltage
Protection connected to pin 8.
circuitry (DRE) that contains under−shoots. An internal
comparator monitors the feed−back (V
is lower than 95.5% of its nominal value, it connects a
200 mA current source to speed−up the charge of the
compensation network. Effectively this appears as a 10x
increase in the loop gain.
sequence until the PFC stage has stabilized (that is when the
“
slow and gradual charge of the pin1 voltage (V
softens the soft start−up sequence. In B version, DRE is
enabled during start−up to speed−up this phase and allow for
the use of smaller V
reduces the power delivery when the output voltage exceeds
105% of its desired level. The NCP1611 does not abruptly
interrupt the switching. Instead, the signal V
controls the on−time is gradually decreased by grounding
pfcOK
The output of the error amplifier is brought to pin 1 for
Given the low bandwidth of the regulation loop, abrupt
The NCP1611 embeds a “dynamic response enhancer”
In A version, DRE is disabled during the start−up
The circuit also detects overshoot and immediately
− It is forced above a voltage drop (V
circuitry.
” signal of the block diagram, is high). The resulting
Figure 67. a) Regulation Block Figure (left), b) Correspondence Between V
CC
capacitors.
pin8
F
) and when V
) by some
CONTROL
TON
http://onsemi.com
pin8
that
)
24
offset down by (V
before it connects to the “V
PWM section. Finally, the output of the regulation block is
a signal (“V
between 0 and a top value corresponding to the maximum
on−time.
The V
the V
Figure 66). Doing so, the on−time smoothly decays to zero
in four to five switching periods typically. If the output
voltage still increases, a second comparator immediately
disables the driver if the output voltage exceeds 107% of its
desired level.
comparators share the same input information. Based on the
typical value of their parameters and if (V
output voltage nominal value (e.g., 390 V), we can deduce:
Current Sense and Zero Current Detection
through the power switch. A current sense resistor (R
is inserted between the MOSFET source and ground to
generate a positive voltage proportional to the MOSFET
current (V
internally reference. When V
Hence, V
The error amplifier OTA and the OVP, UVP and DRE
The NCP1611 is designed to monitor the current flowing
− It is clamped not to exceed 4.0 V + the same V
− Output Regulation Level: V
− Output UVP Level: V
− Output DRE Level: V
− Output Soft OVP Level: V
− Output Fast OVP level: V
REGUL
voltage drop.
F
value is 0.5 V typically.
V
REGUL
CS
pin1
signal applied to the V
). The V
REGUL
features a 4 V voltage swing. V
F
) and scaled down by a resistors divider
” of the block diagram) that varies
CS
CONTROL
voltage is compared to a 500 mV
(V
out,uvp
out,dre
TON
REGUL
CS
out,fovp
and V
exceeds this threshold, the
out,sovp
processing block” and the
TON
)
out,nom
= 95.5% x V
= 12% x V
max
processing block (see
REGUL
= 107% x V
= 105% x V
out,nom
(right)
out,nom
out,nom
pin1
V
CONTROL
out,nom
) is the
out,nom
is then
F
sense
)