M48Z35-70MH1 STMICROELECTRONICS [STMicroelectronics], M48Z35-70MH1 Datasheet - Page 4

• Manufacturer Part Number: M48Z35-70MH1
• Description: 256 Kbit 32Kb x8 ZEROPOWER SRAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M48Z35, M48Z35Y
Table 4. AC Measurement Conditions
Note that Output Hi-Z is defined as the point where data is no longer
driven.
The SOIC and battery packages are shipped sep-
arately in plastic anti-static tubes or in Tape & Reel
form.
For the 28 lead SOIC, the battery package (i.e.
SNAPHAT) part number is "M4Z28-BR00SH1".
The M48Z35/35Y also has its own Power-fail De-
tect circuit. The control circuitry constantly moni-
tors the single 5V supply for an out of tolerance
condition. When V
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable sys-
tem operation brought on by low V
below approximately 3V, the control circuitry con-
nects the battery which maintains data until valid
power returns.
READ MODE
The M48Z35/35Y is in the Read Mode whenever
W (Write Enable) is high, E (Chip Enable) is low.
The device architecture allows ripple-through ac-
cess of data from eight of 264,144 locations in the
static storage array. Thus, the unique address
specified by the 15 Address Inputs defines which
one of the 32,768 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (t
address input signal is stable, providing that the E
and G access times are also satisfied. If the E and
G access times are not met, valid data will be
available after the latter of the Chip Enable Access
time (t
(t
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
4/18
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
GLQV
).
ELQV
) or Output Enable Access time
CC
is out of tolerance, the circuit
AVQV
CC
) after the last
. As V
0 to 3V
1.5V
5ns
CC
falls
Figure 4. AC Testing Load Circuit
ed before t
indeterminate state until t
puts are changed while E and G remain active,
output data will remain valid for Output Data Hold
time (t
Address Access.
WRITE MODE
The M48Z35/35Y is in the Write Mode whenever
W and E are low. The start of a write is referenced
from the latter occurring falling edge of W or E. A
write is terminated by the earlier rising edge of W
or E. The addresses must be held valid throughout
the cycle. E or W must return high for a minimum
of t
able prior to the initiation of another read or write
cycle. Data-in must be valid t
of write and remain valid for t
should be kept high during write cycles to avoid
bus contention; although, if the output bus has
been activated by a low on E and G, a low on W
will disable the outputs t
EHAX
C L includes JIG capacitance
DEVICE
UNDER
AXQX
TEST
from Chip Enable or t
AVQV
) but will go indeterminate until the next
, the data lines will be driven to an
C L = 100pF or
WLQZ
AVQV
5pF
645
DVWH
WHAX
after W falls.
WHDX
. If the Address In-
prior to the end
from Write En-
afterward. G
AI03211
1.75V