HD151BF854_06 RENESAS [Renesas Technology Corp], HD151BF854_06 Datasheet - Page 5

• Manufacturer Part Number: HD151BF854_06
• Description: 2.5 V PLL Clock Buffer for DDR Applicationjpeg
• Manufacturer: RENESAS [Renesas Technology Corp]

HD151BF854
Switching Characteristics
Period jitter
Half period jitter
Cycle to cycle jitter
Static phase offset
Output clock skew
Operating clock frequency
Application clock frequency
Slew rate
Stabilization time
Notes: Target of design, not 100% tested in production.
Rev.5.00 Apr 07, 2006 page 5 of 7
1. The PLL must be able to handle spread spectrum induced skew. (the specification for this frequency
2. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not
3. Application clock frequency indicates a range over which the PLL must meet all timing parameters.
4. Assumes equal wire length and loading on the clock output and feedback path.
5. Static phase offset does not include jitter.
6. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of it’s feedback signal
7. Period jitter defines the largest variation in clock period, around a nominal clock period.
8. Period jitter and half period jitter are separate specifications that must be met independently of each other.
modulation can be found in the latest Intel PC100 Registered DIMM specification)
required to meet the other timing parameters. (Used for low speed system debug.)
to it’s reference signal after power on.
Item
Symbol
f
f
t
CLK(O)
CLK(A)
t
HPER
t
t
PER
sPE
t
CC
sk
Min
1.0
60
80
—
—
—
—
—
—
|120|
|150|
Typ
|75|
|75|
150
166
—
—
—
Max
210
210
2.0
0.1
—
—
—
—
—
Unit
MHz
MHz
V/ns
ms
ps
ps
ps
ps
ps
Ta = 25 C, VDD = AVDD = 2.5V
*7, 8
*8
*4, 5
*1, 2
*1, 3
20% to 80%
*6
Test Conditions & Notes