LPC47M172-NR SMSC [SMSC Corporation], LPC47M172-NR Datasheet - Page 45

• Manufacturer Part Number: LPC47M172-NR
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC [SMSC Corporation]

BIT 5 UNDEFINED
BIT 6 LOW POWER
BIT 7 SOFTWARE RESET
Note:
Note 1:
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
Should be written as a logic “0”.
A logic “1” written to this bit will put the floppy controller into manual low power mode. The floppy
controller clock and data separator circuits will be turned off. The controller will come out of manual low
power mode after a software reset or access to the Data Register or Main Status Register.
This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self
clearing.
Separator circuits will be turned off. The controller will come out of manual low power.
The DSR is Shadowed in the Floppy Data Rate Select Shadow Register, located at the offset 0x19 in the
Power Control/Runtime Register block.
Drive Rate Table (Recommended)
The DRATE and DENSEL values are mapped onto the DRVDEN pins.
DRT1
DRIVE RATE
0
0
0
0
0
0
0
0
1
1
1
1
DRT0
0
0
0
0
1
1
1
1
0
0
0
0
SEL1
DATA RATE
PRECOMP
1
0
0
1
1
0
0
1
1
0
0
1
Table 6.7 - Precompensation Delays
432
111
001
010
011
100
101
110
000
Table 6.8 - Data Rates
SEL0
DATASHEET
1
0
1
0
1
0
1
0
1
0
1
0
00 = 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format
01 = 3-Mode Drive
10 = 2 Meg Tape
1Meg
1Meg
1Meg
2Meg
MFM
Default: See Table 6.10
500
300
250
500
500
250
500
250
PRECOMPENSATION
Page 45
DATA RATE
<2Mbps
Default
125.00
166.67
208.33
250.00
41.67
83.34
0.00
DELAY (NSEC)
250
150
125
250
250
125
250
125
FM
---
---
---
---
Default
2Mbps
104.2
20.8
41.7
62.5
83.3
125
Advanced I/O Controller with Motherboard GLUE Logic
0
DENSEL
1
1
0
0
1
1
0
0
1
1
0
0
DRATE(1)
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
SMSC LPC47M172
Datasheet