LPC47M172-NR SMSC [SMSC Corporation], LPC47M172-NR Datasheet
LPC47M172-NR
Related parts for LPC47M172-NR
LPC47M172-NR Summary of contents
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... Including Multiple Powerdown Modes for Reduced Power Consumption − DMA Enable Logic − Data Rate and Drive Control Registers 480 Address Eight IRQ and Three DMA Options SMSC LPC47M172 LPC47M172 Advanced I/O Controller with Motherboard GLUE Logic Enhanced Digital Data Separator − ...
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... Advanced I/O Controller with Motherboard GLUE Logic Datasheet LPC47M172-NR for 128 MQFP (3.2mm footprint) package 80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123 Copyright © SMSC 2004. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given ...
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... Chapter 1 - General Description, page 12 Rev. 02-23-04 Chapter 12 - Electrical Characteristics, page 196 Rev. 02-20-04 Section 3.1 - Buffer Name Descriptions, page 23 Rev. 02-20-04 Table 3.1 - LPC47M172 Pin Description, page 15 Rev. 02-20-04 Table 6.1 - Super I/O Block Logical Device Number and Addresses, page 33 Rev. 02-20-04 Table 7.31 - Voltage Translation DDC Pins, page 137 Rev. 02-20-04 Figure 7 ...
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... Advanced I/O Controller with Motherboard GLUE Logic Datasheet Table Of Contents LPC47M172 Datasheet Revision History ................................................................................................. 3 Chapter 1 General Description.............................................................................................................. 12 Chapter 2 Pin Layout ............................................................................................................................ 13 Chapter 3 Description of Pin Functions ................................................................................................ 15 3.1 Buffer Name Descriptions ..........................................................................................................................23 3.2 Pins With Internal Resistors .......................................................................................................................24 3.3 Pins That Require External Resistors.........................................................................................................24 3.4 Default State of Pins...................................................................................................................................25 Chapter 4 Block Diagram ...................................................................................................................... 29 Chapter 5 Power and Clock Functionality ...
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... Status Port ..........................................................................................................................................92 7.4.3 Control Port .........................................................................................................................................93 7.4.4 EPP Address Port ...............................................................................................................................94 7.4.5 EPP Data Port 0..................................................................................................................................94 7.4.6 EPP Data Port 1..................................................................................................................................94 7.4.7 EPP Data Port 2..................................................................................................................................94 7.4.8 EPP Data Port 3..................................................................................................................................95 7.5 EPP 1.9 Operation .....................................................................................................................................95 7.5.1 Software Constraints...........................................................................................................................95 SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Advanced I/O Controller with Motherboard GLUE Logic Page 5 DATASHEET Datasheet SMSC LPC47M172 ...
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... Keyboard Status Read ..................................................................................................................116 7.25.6 CPU-to-Host Communication ........................................................................................................116 7.25.7 Host-to-CPU Communication ........................................................................................................116 7.25.8 KIRQ..............................................................................................................................................116 7.25.9 MIRQ .............................................................................................................................................117 7.25.10 External Keyboard and Mouse Interface .......................................................................................117 7.25.11 Keyboard Power Management ......................................................................................................117 7.25.12 Soft Power Down Mode.................................................................................................................117 7.25.13 Hard Power Down Mode ...............................................................................................................117 SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 6 DATASHEET SMSC LPC47M172 ...
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... Logical Device Configuration/Control Registers [0x30-0xFF] ...............................................................183 11.4 Logical Device I/O Address ..................................................................................................................187 11.5 Logical Device Configuration Registers ................................................................................................190 Chapter 12 Electrical Characteristics .................................................................................................... 196 12.1 Maximum Guaranteed Ratings .............................................................................................................196 12.2 Operational DC Characteristics ............................................................................................................196 12.3 Standby Power Requirements ..............................................................................................................201 SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Advanced I/O Controller with Motherboard GLUE Logic Page 7 DATASHEET Datasheet SMSC LPC47M172 ...
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... Figure 7.9 - REF5V_STBY.........................................................................................................................................136 Figure 7.10 - VGA DDC Voltage Translation Circuit...................................................................................................139 Figure 7.11 - SMBUS Isolation Circuit........................................................................................................................140 Figure 7.12 - PWRGD_3V Circuit, Discrete Implementation ......................................................................................142 Figure 7.13 - PWRGD_3V Circuit in LPC47M172 ......................................................................................................142 Figure 7.14 - NFPRST Timing....................................................................................................................................143 Figure 7.15 - SCK_BJT_Gate Circuit .........................................................................................................................144 Figure 7.16 - Backfeed Cut and Latched Backfeed Cut Circuit ..................................................................................145 Figure 7 ...
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... Figure 13.30 - Reseme Reset Sequence ...................................................................................................................223 Figure 14.1 - 128 Pin MQFP Package Outline, 14x20x2.7 Body, 3.2mm Footprint....................................................224 Figure 15.1 - Example XOR Chain Circuitry...............................................................................................................225 List Of Tables Table 3.1 - LPC47M172 Pin Description ......................................................................................................................15 Table 3.2 - Pins with Internal Resistors........................................................................................................................24 Table 3.3 - Pins that Require External Resistors..........................................................................................................24 Table 3.4 - Default State of Pins ..................................................................................................................................26 Table 6 ...
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... Table 9.2 - GPIO Runtime Registers Description, LD_NUM = 0 ................................................................................159 Table 10.1 - Runtime Register Block Runtime Registers Summary ...........................................................................162 Table 10.2 - Runtime Register Block Runtime Registers Description ........................................................................163 Table 11.1 - LPC47M172 Configuration Registers Summary, LD_NUM bit = 0 .........................................................176 Table 11.2 - LPC47M172 Configuration Register Summary, LD_NUM=1..................................................................178 Table 11.3 - Chip Level Registers ..............................................................................................................................180 Table 11 ...
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... Table 13.5 - PWRGD_3V Timing ...............................................................................................................................222 Table 13.6 - CNR CODEC Down Enable Timing .......................................................................................................222 Table 13.7 - Resume Reset Timing............................................................................................................................223 Table 14.1 - 128 Pin MQFP Package Parameters .....................................................................................................224 Table 15.1 - XOR Test Pattern Example....................................................................................................................226 SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Advanced I/O Controller with Motherboard GLUE Logic Page 11 DATASHEET Datasheet SMSC LPC47M172 ...
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... IRQ1 through IRQ15 on the Serial IRQ Interface. The LPC47M172’s Enhanced Digital Data Separator does not require any external filter components and is therefore easy to use and offers lower system costs and reduced board area. The LPC47M172 is register compatible with SMSC’s proprietary 82077AA core. ...
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... VCC 31 nRI 32 SLCT BUSY 35 nACK 36 PD7 37 PD6 38 SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Advanced I/O Controller with Motherboard GLUE Logic LPC47M172 128 PIN QFP Figure 2.1 - LPC47M172 Pin Layout Page 13 DATASHEET Datasheet 102 nCDC_DWN_RST 101 nCDC_DWN_ENAB/GP24 100 nAUD_LINK_RST 99 nIO_PME 98 TEST_EN 97 F_CAP 96 VSS 95 YLW_LED 94 GRN_LED ...
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... Pin 117 is used to select the mode of the logical device numbering. This pin affects the LD_NUM bit in the TEST 7 register (configuration register 0x29), which is used to select logical device numbering in the LPC47M172. See Table 6.1 - Super I/O Block Logical Device Number and Addresses. The pin functions as follows: The pin has an internal pull-down resistor that selects the non-standard SMSC (Intel Compatible) mode. To select this mode, the pin should be left unconnected. This configuration clears the LD_NUM bit to ‘ ...
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... Active low input indicates start of new cycle and termination of broken cycle. 57,59, LAD[3:0] Active high LPC I/O used for multiplexed 61,62 command, address and data bus. SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Table 3.1 - LPC47M172 Pin Description DESCRIPTION POWER AND GROUND PINS (20) See CLOCKS (2) PROCESSOR/HOST LPC INTERFACE (11) Page 15 DATASHEET ...
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... Can be configured as an Open-Drain Output. SMSC/Non-SMSC Register Sets (Rev. 02-27-04) BUFFER DESCRIPTION NAME (NOTE 2) PCI_I OD8 FDD INTERFACE (14) IS O12 O12 O12 Page 16 DATASHEET PWR WELL NOTES (NOTE 3) VCC VTR VCC VCC VCC VCC VCC VCC VCC SMSC LPC47M172 ...
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... SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Advanced I/O Controller with Motherboard GLUE Logic BUFFER DESCRIPTION (NOTE 2) O12 O12 O12 O12 IS O12 O12 SERIAL PORT 1 INTERFACE ( Page 17 DATASHEET Datasheet PWR NAME WELL NOTES (NOTE 3) VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC SMSC LPC47M172 ...
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... Receiver serial data input. 120 TXD2 Transmit serial data output. SMSC/Non-SMSC Register Sets (Rev. 02-27-04) BUFFER DESCRIPTION (NOTE 2) O8 O12 SERIAL PORT 2 INTERFACE (8) IPD ISPD_400 O12 Page 18 DATASHEET PWR NAME WELL NOTES (NOTE 3) VCC VCC VCC VCC VTR 6 VTR 6, 10 VCC VCC SMSC LPC47M172 ...
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... IOP14 IOP14 IOP14 IOP14 IOP14 IOP14 IOP14 IOP14 Page 19 DATASHEET Datasheet BUFFER PWR NAME WELL NOTES (NOTE 2) (NOTE 3) VCC 10 VCC VCC 10 VCC VCC 10 VCC 10 VCC 9 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC SMSC LPC47M172 ...
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... KEYBOARD/MOUSE INTERFACE (6) IOD24 IOD24 IOD24 IOD24 OD8 OD8 GLUE PINS (29) OD8 OD12 ISPU_400 ISPU_400 ISPU_400 Page 20 DATASHEET BUFFER PWR NAME WELL NOTES (NOTE 2) (NOTE 3) VCC VCC VCC VCC VCC VCC VCC 6 VCC VCC 6 VCC 7 VCC 7 VCC 3 VCC 3 VCC VCC VCC SMSC LPC47M172 ...
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... ISO8 Page 21 DATASHEET Datasheet PWR WELL NOTES (NOTE 3) VTR VTR VTR VTR 3 VTR VTR 3 VTR 3 VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR 6 VTR VTR VTR VTR VTR VTR VTR VTR 6 SMSC LPC47M172 ...
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... POR) until it is selected via the IR MUX bits and serial port 2 is enabled by setting the activate bit, at which SMSC/Non-SMSC Register Sets (Rev. 02-27-04) DESCRIPTION TEST (1) NO CONNECT (1) See Note11 Page 22 DATASHEET BUFFER PWR NAME WELL NOTES (NOTE 2) (NOTE 3) IO8 VTR 6 IO8 VTR 6 IO8 VTR 6 IPD VTR IPD - 11 SMSC LPC47M172 The ...
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... Note 11: Pin 117 is used to select the mode of the logical device numbering. This pin affects the LD_NUM bit in the TEST 7 register (configuration register 0x29), which is used to select logical device numbering in the LPC47M172. See Table 6.1 - Super I/O Block Logical Device Number and Addresses. The pin has an internal pull-down resistor that selects the non-SMSC (Intel Compatible) mode. To select this mode, the pin should be left unconnected ...
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... Pull-up required if used as Open-Drain Output. 10 kohm 10 kohm Pull-up to VCC. 10 kohm 10 kohm 10 kohm 10 kohm 10 kohm 10 kohm 1 kohm Pull-up to VCC 1 kohm Pull-up to VCC 1 kohm Pull-up to VCC 1 kohm Pull-up to VCC 10 kohm Pull-up to VCC 1 kohm Pull-up to VCC5V 1 kohm Pull-up to V_5P0_STBY Page 24 DATASHEET NOTES NOTES SMSC LPC47M172 ...
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... Pull-up to VCC 4.7 kohm Pull-up to VCC 4.7 kohm Pull-up to VCC 2.2 kohm Pull-up to VCC5V 2.2 kohm Pull-up to VCC5V 2.7 kohm Pull-up to VCC 2.7 kohm Pull-up to VTR 2.7 kohm Pull-up to VCC 2.7 kohm Pull-up to VTR 220 ohm Pull-up to VTR design-dependant Pull-up to appropriate voltage (not to exceed 5V) Page 25 DATASHEET Datasheet NOTES SMSC LPC47M172 ...
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... This pin requires external pull VCC5V This pin is internally pulled down to VSS until Serial Port 2 is enabled. This pin is internally pulled down to VSS until Serial Port 2 is enabled. This pin is internally pulled down to VSS until Serial Port 2 is enabled. SMSC LPC47M172 ...
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... This pin is pulled up internally This pin requires external pull V_5P0_STBY. This pin requires external pull V_5P0_STBY. This pin is pulled up internally This pin is pulled up internally This pin is pulled up internally Requires external pull-up to VCC5V Requires external pull-up to V_5P0_STBY This pin is pulled up internally SMSC LPC47M172 ...
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... VCC5V. The DDC and GPIO functions are multiplexed on the same pin with DDC as the default function. DDC function requires external pull-up to VCC. Test Mode pin. This pin has internally pull-down to VSS. External pull-up required to enable the test mode. SMSC LPC47M172 ...
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... V_5P0_STBY Configuration Registers nPCI_RESET SMSC PROPRIETARY 82077 COMPATIBLE VERTICAL FLOPPYDISK VGA SMBus CONTROLLER CORE Voltage Isolation Translation Figure 4.1 - LPC47M172 Block Diagram Page 29 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet XOR-Chain PD[7:0] BUSY, SLCT, PE, Multi-Mode nERROR, nACK Parallel Port with ChiProtect TM nSTROBE, nINITP, ...
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... Volt Operation / 5 Volt Tolerance The LPC47M172 is a 3.3 Volt part intended solely for 3.3V applications. Non-LPC bus pins are 5V tolerant; that is, the operating input voltage is 5.5V max, and the I/O buffer output pads are backdrive protected (they do not impose a load on any external VCC powered circuitry). ...
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... LED blink and wake on specific key function. 5.5.1 Indication of 32KHZ Clock There is a bit to indicate whether or not the 32kHz clock input is connected to the LPC47M172. This bit is located at bit 0 of the CLOCKI32 configuration register at 0xF0 in Logical Device A (see Table 11.14). This register is powered by VTR and reset on a VTR POR. ...
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... VCC cycles on and off. When the internal PWRGOOD signal is “1” (active), VCC > 2.3V (nominal), and the LPC47M172 host interface is active. When the internal PWRGOOD signal is “0” (inactive), VCC <= 2.3V (nominal), and the LPC47M172 host interface is inactive; that is, LPC bus reads and writes will not be decoded. ...
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... Chapter 6 Functional Description The following sections describe the functional blocks located in the LPC47M172 (see Figure 4.1). The various Super I/O components are described in the following sections and their registers are implemented as typical Plug-and-Play components (see section Chapter 11 − Configuration on page 173). 6.1 Super I/O Registers Table 6 ...
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... These fields are driven onto the LAD[3:0] signal lines to communicate address, control and data information over the LPC bus between the host and the LPC47M172. See the Low Pin Count (LPC) Interface Specification Revision 1.0 from Intel, Section 4.2 for definition of these fields. ...
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... NLFRAME Usage nLFRAME is used by the host to indicate the start of cycles and the termination of cycles due to an abort or time-out condition. This signal used by the LPC47M172 to know when to monitor the bus for a cycle. This signal is used as a general notification that the LAD[3:0] lines contain information relative to the start or stop of a cycle, and that the LPC47M172 monitors the bus to determine whether the cycle is intended for it ...
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... SYNC pattern upon recognizing the cycle. The host immediately drives the sync pattern for write cycles. If the LPC47M172 needs to assert wait states, it does so by driving 0101 or 0110 on LAD[3:0] until it is ready, at which point it will drive 0000 or 1001. The LPC47M172 will choose to assert 0101 or 0110, but not switch between the two patterns. ...
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... The LPC47M172 reports errors via the LAD[3:0] = 1010 SYNC encoding. If the host was reading data from the LPC47M172, data will still be transferred in the next two nibbles. This data may be invalid, but it will be transferred by the LPC47M172. If the host was writing data to the LPC47M172, the data had already been transferred. ...
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... R/W Digital Output Register (DOR) 373 R/W Tape Drive Register (TDR) 374 R Main Status Register (MSR) 374 W Data Rate Select Register (DSR) 375 R/W Data (FIFO) 376 Reserved 377 R Digital Input Register (DIR) 377 W Configuration Control Register (CCR) Page 38 DATASHEET REGISTER SMSC LPC47M172 ...
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... Active low status indicating the direction of head movement. A logic “0” indicates inward direction; a logic “1” indicates outward direction. SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Advanced I/O Controller with Motherboard GLUE Logic STEP nTRK0 HDSEL 0 N DRQ STEP TRK0 nHDSEL INDEX F N/A 1 Page 39 DATASHEET Datasheet nINDX nWP DIR N/A N nDIR N/A N/A 1 SMSC LPC47M172 ...
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... Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. BIT 2 WRITE GATE Active high status of the WGATE disk interface output. SMSC/Non-SMSC Register Sets (Rev. 02-27-04 DRIVE WDATA RDATA SEL0 TOGGLE TOGGLE Page 40 DATASHEET WGATE MOT MOT EN1 EN0 SMSC LPC47M172 ...
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... BIT 7 nDRV2 Active low status of the DRV2 disk interface input. Note: This function is not supported. SMSC/Non-SMSC Register Sets (Rev. 02-27-04 nDS0 WDATA RDATA F/F F Page 41 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet WGATE nDS3 nDS2 F SMSC LPC47M172 ...
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... DRIVE DOR VALUE 0 1CH 1 2DH DRIVE SELECT OUTPUTS (ACTIVE LOW) Bit 0 nDS1 nDS0 Page 42 DATASHEET nRESET DRIVE DRIVE SEL1 SEL0 MOTOR ON OUTPUTS (ACTIVE LOW) nMTR1 nMTR0 nBIT 5 nBIT 4 nBIT 5 nBIT 4 nBIT 5 nBIT 4 SMSC LPC47M172 ...
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... BIT 6 MOTOR ENABLE 2 The MTR2 disk interface output is not supported in the LPC47M172. BIT 7 MOTOR ENABLE 3 The MTR3 disk interface output is not supported in the LPC47M172. 6.4.6 Tape Drive Register (TDR) Address 3F3 READ/WRITE The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to assign tape support to a particular drive during initialization ...
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... L0-CRF2 – L0-CRF2 – L0-CRF2 – L0-CRF2 – PRE- PRE- PRE- COMP2 COMP1 COMP0 Page 44 DATASHEET Bit 4 L0-CRF2 – B0 L0-CRF2 – B2 L0-CRF2 – B4 L0-CRF2 – DRATE DRATE SEL1 SEL0 1 0 SMSC LPC47M172 ...
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... Vertical Format 01 = 3-Mode Drive Meg Tape Page 45 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet 0 20.8 41.7 62.5 83.3 125 DRATE(1) DENSEL SMSC LPC47M172 ...
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... DRATE0 PRECOMPENSATION DATA RATE DELAYS 2 Mbps 20 Mbps 41.67 ns 500 Kbps 125 ns 300 Kbps 125 ns 250 Kbps 125 NON CMD Reserved Reserved DMA BUSY Page 46 DATASHEET DRIVE TYPE 4/2/1 MB 3.5” 2/1 MB 5.25” FDDS 2/1.6/1 MB 3.5” (3-MODE) PS DRV1 DRV0 BUSY BUSY SMSC LPC47M172 ...
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... MBPS DATA RATE 118.5 us MAXIMUM DELAY TO SERVICING AT 500 KBPS DATA RATE 126 1 238.5 us Page 47 DATASHEET Datasheet This maintains PC/AT SMSC LPC47M172 ...
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... COND. SMSC/Non-SMSC Register Sets (Rev. 02-27-04 N/A N/A N/A N N/A N/A N/A N DMAEN NOPREC DRATE Page 48 DATASHEET N/A N/A N DRATE DRATE nHIGH SEL1 SEL0 DENS N/A N DRATE SEL1 SEL0 SMSC LPC47M172 ...
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... Model 30 register mode. Unaffected by software reset. SMSC/Non-SMSC Register Sets (Rev. 02-27-04 N/A N/A N/A N N/A N/A N/A N/A Page 49 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet DRATE DRATE SEL1 SEL0 N NOPREC DRATE DRATE SEL1 SEL0 N SMSC LPC47M172 ...
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... The FDC detected a CRC error in either the ID field or the data field of a sector. Overrun/ Becomes set if the FDC does not receive CPU or DMA service within the required time interval, resulting in Underrun data overrun or underrun. Unused. This bit is always "0". Page 50 DATASHEET SMSC LPC47M172 ...
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... Track 0 Indicates the status of the TRK0 pin. Unused. This bit is always "1". Head Address Indicates the status of the HDSEL pin. Drive Select Indicates the status of the DS1, DS0 pins. Page 51 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet SMSC LPC47M172 ...
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... DMA transfers are enabled with the Specify command and are initiated by the FDC by activating a DMA request cycle. DMA read, write and verify cycles are supported. The FDC supports two DMA transfer modes: Single Transfer and Burst Transfer. Burst mode is enabled via FDC Logical Device -CRF0-Bit[1]. SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 52 DATASHEET SMSC LPC47M172 ...
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... Non-DMA Mode - Transfers from the FIFO to the Host This part does not support non-DMA mode. Non-DMA Mode - Transfers from the Host to the FIFO This part does not support non-DMA mode. SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Advanced I/O Controller with Motherboard GLUE Logic Page 53 DATASHEET Datasheet SMSC LPC47M172 ...
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... Interrupt Status command which returns an invalid command error. Refer to Table 6.16 for explanations of the various symbols used. Table 6.17 lists the required parameters and the results associated with each command that the FDC is capable of performing. SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 54 DATASHEET SMSC LPC47M172 ...
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... With this flag set, a multitrack read or write operation will automatically continue to the first sector under head 1 when the FDC finishes operating on the last sector under head 0. Page 55 DATASHEET Datasheet SMSC LPC47M172 ...
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... Mbit data rate. Refer to the SPECIFY command for actual delays. Registers within the FDC which store status information after a command has been executed. This status information is available to the host during the result phase after command execution. Alters timing allow for pre-erase loads in perpendicular drives. Page 56 DATASHEET SMSC LPC47M172 ...
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... FDD and system. Status information after Com- mand execution. Sector ID information after Command execution. REMARKS 0 Command Codes Sector ID information prior to Command execution. Data transfer between the FDD and system. Status information after Com- mand execution. Sector ID information after Command execution. SMSC LPC47M172 ...
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... FDD and system. Status information after Com- mand execution. Sector ID information after Command execution. D0 REMARKS 1 Command Codes DS0 Sector ID information prior to Command execution. Data transfer between the FDD and system. Status information after Command execution. Sector ID information after Command execution. SMSC LPC47M172 ...
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... EOT. Status information after Command execution. Sector ID information after Command execution. D0 REMARKS 0 Command Codes DS0 Sector ID information prior to Command execution. No data transfer takes place. Status information after Command execution. Sector ID information after Command execution. SMSC LPC47M172 ...
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... DS0 Bytes/Sector Sectors/Cylinder Gap 3 Filler Byte Input Sector Parameters FDC formats an entire cylinder Status information after Command execution D0 REMARKS 1 Command Codes DS0 Head retracted to Track 0 Interrupt. REMARKS Command Codes Status information at the end of each seek operation. REMARKS 1 Command Codes SMSC LPC47M172 ...
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... Page 61 DATASHEET Datasheet D0 REMARKS 0 Command Codes DS0 Status information about FDD D0 REMARKS 1 Command Codes DS0 Head positioned over proper cylinder on diskette REMARKS 1 1 Configure Information REMARKS 1 DS0 D1 D0 REMARKS 1 0 *Note: Registers placed in FIFO HUT ND GAP WGATE SMSC LPC47M172 ...
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... Cylinder is stored in Data Register Status information after Command execution. Disk status after the Command has completed D0 REMARKS 0 Command Codes WGATE D0 REMARKS Invalid Command Codes (NoOp – FDC goes into Standby State) ST0 = 80H D1 D0 REMARKS Command Codes SMSC LPC47M172 ...
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... MT bit and EOT byte. Refer to Table 6.19. SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Advanced I/O Controller with Motherboard GLUE Logic Upon receipt of the TC cycle implied TC (FIFO Table 6.18 - Sector Sizes N SECTOR SIZE 00 128 bytes 01 256 bytes 02 512 bytes 03 1024 bytes .. … Kbytes Page 63 DATASHEET Datasheet SMSC LPC47M172 ...
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... RESULTS SECTOR CM BIT OF READ? ST2 SET? Yes No Yes Yes Yes No No Yes Page 64 DATASHEET DESCRIPTION OF RESULTS Normal termination. Address not incremented. Next sector not searched for. Normal termination. Normal termination. Sector not read (“skipped”). SMSC LPC47M172 ...
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... Page 65 DATASHEET Datasheet DESCRIPTION OF RESULTS Address not incremented. Next sector not searched for. Normal termination. Normal termination. Sector not read (“skipped”). Normal termination. The FDC compares the SMSC LPC47M172 ...
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... MT and EC versus SC and EOT value. Definitions: # Sectors Per Side = Number of formatted sectors per each side of the disk. # Sectors Remaining = Number of formatted sectors left which can be read, including side 1 of the disk set to “1”. SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 66 DATASHEET SMSC LPC47M172 ...
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... Result Phase Valid Unsuccessful Termination Result Phase Invalid Successful Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid Successful Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid Successful Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid Page 67 DATASHEET Datasheet SMSC LPC47M172 ...
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... ... ... 256 256 512 ... ... 128 256 512 256 SMSC LPC47M172 ...
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... FDC is in the BUSY state, but during the execution phase the NON-BUSY state. At this time, another Seek or Recalibrate command may be issued, and in this manner, parallel seek operations may be done four drives at once. SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Advanced I/O Controller with Motherboard GLUE Logic Page 69 DATASHEET Datasheet SMSC LPC47M172 ...
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... Status is not issued, the drive will continue to be BUSY and may affect the operation of the next command. SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Table 6.25 - Interrupt Identification SE IC INTERRUPT DUE Polling 1 00 Normal termination of Seek or Recalibrate command Abnormal termination of Seek or Recalibrate 1 01 command Page 70 DATASHEET SMSC LPC47M172 ...
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... HLT 1M 500K 128 256 126 252 127 254 Page 71 DATASHEET Datasheet SRT 500K 300K 250K 1.67 2 300K 250K 426 512 3 420 504 423 508 SMSC LPC47M172 ...
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... It is the user’s responsibility to compensate FDC functions (precompensation track number) when accessing tracks greater than 255. The FDC does not keep track SMSC/Non-SMSC Register Sets (Rev. 02-27-04) DIR ACTION 0 Step Head Out 1 Step Head In Page 72 DATASHEET SMSC LPC47M172 ...
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... The information provided here is just for background purposes and is not needed for normal operation. Once the Perpendicular Mode command is invoked, FDC software behavior from the user standpoint is unchanged. SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Advanced I/O Controller with Motherboard GLUE Logic Page 73 DATASHEET Datasheet SMSC LPC47M172 ...
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... LOCK command. This byte reflects the value of the LOCK bit set by the command byte. SMSC/Non-SMSC Register Sets (Rev. 02-27-04) LENGTH OF MODE GAP2 FORMAT FIELD 0 Conventional 22 Bytes 1 Perpendicular 22 Bytes (500 Kbps) 0 Reserved 22 Bytes (Conventional) 1 Perpendicular 41 Bytes (1 Mbps) Page 74 DATASHEET PORTION OF GAP 2 WRITTEN BY WRITE DATA OPERATION 0 Bytes 19 Bytes 0 Bytes 38 Bytes SMSC LPC47M172 ...
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... Compatibility The LPC47M172 was designed with software compatibility in mind fully backwards- compatible solution with the older generation 765A/B disk controllers. The FDC also implements on-board registers for compatibility with the PS/2, as well as PC/AT and PC/XT, floppy disk controller subsystems. After a ...
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... Disabling the interrupt system inhibits the Interrupt Identification Register and disables any Serial Port interrupt out of the LPC47M172. All other system functions operate in their normal manner, including the Line Status and MODEM Status Registers. The contents of the Interrupt Enable Register are described below ...
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... They are in descending order of priority: 1. Receiver Line Status (highest priority) 2. Received Data Ready 3. Transmitter Holding Register Empty 4. MODEM Status (lowest priority) SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Advanced I/O Controller with Motherboard GLUE Logic Page 77 DATASHEET Datasheet Clearing this bit to a logic “0” SMSC LPC47M172 ...
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... Overrun Error, Receiver Line Parity Error, Highest Status Framing Error or Break Interrupt Received Data Receiver Data Second Available Available Page 78 DATASHEET INTERRUPT RESET CONTROL None - Reading the Line Status Register Read Receiver Buffer or the FIFO drops below the trigger level. SMSC LPC47M172 ...
Page 79
... Serial Data BIT 1 BIT 0 WORD LENGTH Bits Bits Bits Bits Page 79 DATASHEET Datasheet Reading the Receiver Buffer Register Reading the IIR Register (if Source of Interrupt) or Empty Writing the Transmitter Holding Register Reading the MODEM Status Register Detect SMSC LPC47M172 ...
Page 80
... This bit controls the Request To Send (nRTS) output. Bit 1 affects the nRTS output in a manner identical to that described above for bit 0. SMSC/Non-SMSC Register Sets (Rev. 02-27-04) NUMBER OF BIT 2 WORD LENGTH STOP BITS bits 1 bits bits bits 2 Page 80 DATASHEET SMSC LPC47M172 ...
Page 81
... The PE is set to a logic “1” upon detection of a parity error and is reset to a logic “0” whenever the Line Status Register is read. In the FIFO mode this error is SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Advanced I/O Controller with Motherboard GLUE Logic Page 81 DATASHEET Datasheet SMSC LPC47M172 ...
Page 82
... These bits are set to logic “1” whenever a control input from the MODEM changes state. They are reset to logic “0” whenever the MODEM Status Register is read. SMSC/Non-SMSC Register Sets (Rev. 02-27-04) In the FIFO mode this bit is set whenever the Page 82 DATASHEET This error is indicated when the SMSC LPC47M172 ...
Page 83
... Divisor Latches bit Baud counter is immediately loaded. This prevents long counts on initial load loaded into the BRG registers the output divides the clock by the number SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Advanced I/O Controller with Motherboard GLUE Logic Page 83 DATASHEET Datasheet It is intended as a SMSC LPC47M172 ...
Page 84
... Character timeout and RCVR FIFO trigger level interrupts have the same priority as the current received data available interrupt; XMIT FIFO empty has the same priority as the current transmitter holding register empty interrupt. SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 84 DATASHEET SMSC LPC47M172 ...
Page 85
... Page 85 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet HIGH 1 2 SPEED BIT SMSC LPC47M172 ...
Page 86
... Bits low; Bits input RESET High RESET/Read LSR Low RESET/Read RBR Low RESET/ReadIIR/Write THR Low RESET High RESET High RESET High RESET High RESET/ All Bits Low FCR1*FCR0/_FCR0 RESET/ All Bits Low FCR1*FCR0/_FCR0 Page 86 DATASHEET RESET STATE SMSC LPC47M172 ...
Page 87
... Carrier Send (CTS) Ready (RI) Detect (DSR) (DDCD) Bit 3 Bit 4 Bit 5 Bit 6 Bit 3 Bit 4 Bit 5 Bit 6 Bit 11 Bit 12 Bit 13 Bit 14 SMSC LPC47M172 BIT 7 Data Bit 7 Data Bit 7 0 FIFOs Enabled (Note 6) RCVR Trigger MSB Divisor Latch Access Bit (DLAB) 0 Error in RCVR FIFO ...
Page 88
... Writing a one to this bit has no effect. DMA modes are not supported in this chip. Note 7 The UART1 and UART2 FCR’s are shadowed in the UART1 FIFO Control Shadow Register (runtime Note 8 register at offset 0x20) and UART2 FIFO Control Shadow Register (runtime register at offset 0x21). SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 88 DATASHEET SMSC LPC47M172 ...
Page 89
... CPU reads the Rx FIFO or another character enters it. These FIFO related features allow optimization of CPU/UART transactions and are especially useful given the higher baud rate capability (256 kbaud). SMSC LPC47M172 Advanced I/O Controller with Motherboard GLUE Logic Page 89 SMSC/Non-SMSC Register Sets (Rev ...
Page 90
... Parallel Port The LPC47M172 incorporates an IBM XT/AT compatible parallel port. This supports the optional PS/2 type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the Configuration Registers for information on disabling, power down, changing the base address of the parallel port, and selecting the mode of operation ...
Page 91
... PD0 PD1 PORT 3 Note 1: These registers are available in all modes. Note 2: These registers are only available in EPP mode. SMSC LPC47M172 BASE ADDRESS + 00H EPP DATA PORT 0 BASE ADDRESS + 01H EPP DATA PORT 1 BASE ADDRESS + 02H EPP DATA PORT 2 BASE ADDRESS + 03H ...
Page 92
... PD<0:7> PData<0:7> nACK Intr BUSY nWait PE (User Defined) SLCT (User Defined) nALF nDatastb nERROR (User Defined) nINITP nRESET nSLCTIN nAddrstrb Page 92 DATASHEET ECP nStrobe PData<0:7> nAck Busy, PeriphAck(3) PError, nAckReverse (3) Select nAutoFd, HostAck(3) nFault (1) nPeriphRequest (3) nInit(1) nReverseRqst(3) nSelectIn(1,3) This SMSC LPC47M172 ...
Page 93
... This bit is output onto the nINITP output without inversion. BIT 3 SLCTIN - PRINTER SELECT INPUT This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects the printer; a logic 0 means the printer is not selected. SMSC LPC47M172 Advanced I/O Controller with Motherboard GLUE Logic Page 93 SMSC/Non-SMSC Register Sets (Rev. 02-27-04) ...
Page 94
... The EPP Data Port 2 is located at an offset of ‘06H’ from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode. SMSC/Non-SMSC Register Sets (Rev. 02-27-04) In printer mode, the direction is always out Page 94 DATASHEET SMSC LPC47M172 ...
Page 95
... The chip deasserts nDATASTB or nADDRSTRB, this marks the beginning of the termination phase has not already done so, the peripheral should latch the information byte now. SMSC LPC47M172 Advanced I/O Controller with Motherboard GLUE Logic Page 95 SMSC/Non-SMSC Register Sets (Rev. 02-27-04) ...
Page 96
... Before an EPP cycle is executed, the software must ensure that the control register bits D0, D1 and D3 are set to zero. Also, bit D5 (PCD logic “0” for an EPP write or a logic “1” for and EPP read. SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 96 DATASHEET SMSC LPC47M172 ...
Page 97
... Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle. EPP SIGNAL EPP NAME nWRITE nWrite PD<0:7> Address/Data INTR Interrupt SMSC LPC47M172 Advanced I/O Controller with Motherboard GLUE Logic Table 7.2 - EPP Pin Descriptions TYPE EPP DESCRIPTION O This signal is active low. It denotes a write operation. I/O Bi-directional EPP byte wide address and data bus. I This signal is active high and positive edge triggered ...
Page 98
... O This signal is active low. When driven active, the EPP device is reset to its initial operational mode. O This signal is active low used to denote address read or write operation. I Same as SPP mode. I Same as SPP mode. I Same as SPP mode. Page 98 DATASHEET SMSC LPC47M172 ...
Page 99
... The port also supports run length encoded (RLE) decompression (required) in hardware. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the SMSC LPC47M172 Advanced I/O Controller with Motherboard GLUE Logic D5 ...
Page 100
... Sets the transfer direction (asserted = reverse, deasserted = forward). This pin is driven low to place the channel in the reverse direction. The peripheral is only allowed to drive the bi-directional data bus while in ECP Mode and HostAck is low and nSelectIn is high. Always deasserted in ECP mode. Page 100 DATASHEET SMSC LPC47M172 ...
Page 101
... ECP port transmits this byte to the peripheral automatically. The operation of this register is only defined for the forward direction (direction is 0). Refer to the ECP Parallel Port Forward Timing Diagram, located in the Timing Diagrams section of this data sheet . SMSC LPC47M172 Advanced I/O Controller with Motherboard GLUE Logic Table 7.4 - ECP Register Definitions ...
Page 102
... The interrupt request enable bit when set to a high level may be used to from the Parallel Port to the CPU due to a low to high transition on the nACK input. Refer to the description of the interrupt under Operation, Interrupts. SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 102 DATASHEET enable interrupt requests SMSC LPC47M172 ...
Page 103
... The writeIntrThreshold can be determined by starting with a full tFIFO, setting the direction bit to 0 and emptying it a byte at a time until serviceIntr is set. This may generate a spurious interrupt, but will indicate that the threshold has been reached. SMSC LPC47M172 Advanced I/O Controller with Motherboard GLUE Logic Page 103 SMSC/Non-SMSC Register Sets (Rev ...
Page 104
... Table 7.8 - Programming for Configuration Register B (Bits 2:0) 7.12.9 ecr (Extended Control Register) ADDRESS OFFSET = 402H Mode = all This register controls the extended ECP parallel port functions. BITS 7,6,5 These bits are Read/Write and select the Mode. SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 104 DATASHEET SMSC LPC47M172 ...
Page 105
... The FIFO cannot accept another byte or the FIFO is completely full. 0: The FIFO has at least 1 free byte. BIT 0 empty Read only 1: The FIFO is completely empty. 0: The FIFO contains at least 1 byte of data. SMSC LPC47M172 Advanced I/O Controller with Motherboard GLUE Logic Page 105 SMSC/Non-SMSC Register Sets (Rev. 02-27-04) DATASHEET Datasheet ...
Page 106
... Table 7.8 - Programming for Configuration Register B (Bits 2:0) DMA SELECTED SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Table 7.6 - Extended Control Register MODE CONFIG REG B IRQ SELECTED BITS 5:3 15 110 14 101 11 100 10 011 9 010 7 001 5 111 All Others 000 CONFIG REG B BITS 2:0 3 011 2 010 1 001 All Others 000 Page 106 DATASHEET SMSC LPC47M172 ...
Page 107
... ECP read data byte and attempt to fill the FIFO. Bytes may then be read from the ecpDFifo as long not empty. ECP transfers may also be accomplished (albeit slowly) by handshaking individual bytes under program control in mode = 001, or 000. SMSC LPC47M172 Advanced I/O Controller with Motherboard GLUE Logic Page 107 SMSC/Non-SMSC Register Sets (Rev. 02-27-04) ...
Page 108
... Pin Definition The drivers for nStrobe, nAutoFd, nInit and nSelectIn are open-drain in mode 000 and are push-pull in all other modes. SMSC/Non-SMSC Register Sets (Rev. 02-27-04) D7 D[6:0] 0 Run-Length Count (0-127) (mode 0011 0X00 only) 1 Channel Address (0-127) Page 108 DATASHEET SMSC LPC47M172 ...
Page 109
... This is the desired case for use with a “fast” system. A high value of threshold (i.e. 12) is used with a “sluggish” system by affording a long latency period after a service request, but results in more frequent service requests. SMSC LPC47M172 After a reset, the FIFO is disabled. Page 109 ...
Page 110
... In the reverse direction an interrupt occurs when serviceIntr is 0 and readIntrThreshold bytes are available in the FIFO this time the FIFO is full it can be emptied completely in a single burst, otherwise readIntrThreshold bytes may be read from the FIFO in a single burst. readIntrThreshold =(16-<threshold>) data bytes in FIFO SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 110 DATASHEET SMSC LPC47M172 ...
Page 111
... Serial IRQ The LPC47M172 supports the serial interrupt to transmit interrupt information to the host system. The serial interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0. 7.23.1 Timing Diagrams For SER_IRQ Cycle A) Start Frame timing with source sampled a low pulse on IRQ1 ...
Page 112
... This makes a total low pulse width of four to eight clocks. Finally, the Host Controller will drive the SER_IRQ back high for one clock, then tri-state. If LPC47M172 detects any transition on an IRQ/Data line for which it is responsible, it initiates a Start Frame in order to update the Host Controller unless the SER_IRQ is already in an SER_IRQ Cycle and the ...
Page 113
... SER_IRQ Data Frame Once a Start Frame has been initiated, the LPC47M172 will watch for the rising edge of the Start Pulse and start counting IRQ/Data Frames from there. Each IRQ/Data Frame is three clocks: Sample phase, Recovery phase, and Turn-around phase. During the Sample phase the LPC47M172 drives the SER_IRQ low, if and only if, its last detected IRQ/Data value was low ...
Page 114
... Serial IRQ stream by writing these bits to ‘0’ overrides other interrupt sources for the Serial IRQ stream. No other functional logic in the LPC47M172 sets bits in these registers. The asserted interrupt in the Serial IRQ stream from registers INT_GEN1 and INT_GEN2 is removed by writing the corresponding bit to ‘1’. ...
Page 115
... Port 21 is used to create a GATEA20 signal from the LPC47M172. 7.25.1 Keyboard Interface The LPC47M172 LPC interface is functionally compatible with the 8042 style host interface. It consists of the D0-7 data signals; the read and write signals and the Status register, Input Data register, and Output Data register ...
Page 116
... This bit read only register. Refer to the description of the Status Register for more information. 7.25.6 CPU-to-Host Communication The LPC47M172 CPU can write to the Output Data register via register DBB. A write to this register automatically sets Bit 0 (OBF) in the Status register. See Table 7.11. ...
Page 117
... If “EN FLAGS” has been executed and P25 is set to a one:; IBF is inverted and gated onto MIRQ. The MIRQ signal can be connected to system interrupt to signify that the LPC47M172 CPU has read the DBB register. If “EN FLAGS” has not been executed, MIRQ is controlled by P25, Writing a zero to P25 forces MIRQ low, a high forces MIRQ high ...
Page 118
... Status Register This register is cleared on a reset. This register is read-only for the Host and read/write by the LPC47M172 CPU. UD Writable by LPC47M172 CPU. These bits are user-definable. C/D (Command Data)-This bit specifies whether the input data register contains data or a command (0 = data command). During a host data/command write operation, this bit is set to “ ...
Page 119
... External Clock Signal The LPC47M172 Keyboard Controller clock source MHz clock generated from a 14.318 MHz clock. The reset pulse must last for at least 24 16 MHz clock periods. The pulse-width requirement applies to both internally (Vcc POR) and externally generated reset signals. In powerdown mode, the external clock signal is not loaded by the chip ...
Page 120
... Location 92h Default Value 24h Attribute Read/Write Size 8 bits PORT 92 REGISTER FUNCTION Reserved. Returns 00 when read Reserved. Returns a 1 when read Reserved. Returns a 0 when read Reserved. Returns a 0 when read Reserved. Returns a 1 when read Page 120 DATASHEET SMSC LPC47M172 ...
Page 121
... Writing bit 1 of the Port 92 Register forces ALT_A20 high. ALT_A20 high drives nA20M to the CPU high, regardless of the state of A20GATE from the keyboard controller. Upon reset, this signal is driven low. Latches On Keyboard and Mouse IRQs The implementation of the latches on the keyboard and mouse interrupts is shown following. SMSC LPC47M172 14us ~ ~ 6us KRST ...
Page 122
... The KLATCH and MLATCH bits are located in the KRST_GA20 register, in Keyboard Logical Device at 0xF0. SMSC/Non-SMSC Register Sets (Rev. 02-27-04) KLATCH Bit VCC D Q KINT CLR RD 60 Figure 7.2 - Keyboard Latch MLATCH Bit VCC D Q MINT CLR RD 60 Figure 7.3 - Mouse Latch Page 122 DATASHEET KINT new MINT new SMSC LPC47M172 ...
Page 123
... PME events. The LPC47M172 has a mode to select the isolation of keyboard and mouse clock and data signals by hardware when the nLPCPD signal is active and/or when the isolation bits are set by software ...
Page 124
... BIOS software needs to clear these PME status bits after power-up. 7.27 General Purpose I/O The LPC47M172 provides a set of flexible Input/Output control functions to the system designer through the 13 independently programmable General Purpose I/O pins (GPIO). The GPIO pins can perform basic SMSC/Non-SMSC Register Sets (Rev. 02-27-04) ...
Page 125
... Runtime Registers section when LD_NUM=0 and Chapter 10 Runtime Register Block Runtime Registers sections when LD_NUM=1). The GPIO ports with their alternate functions and configuration state register addresses are listed in Table 7.17. SMSC LPC47M172 Advanced I/O Controller with Motherboard GLUE Logic Table 7.16 - GPIO Summary ...
Page 126
... Pin is a non-inverted output Pin is an inverted output Pin is a non-inverted input Pin is an inverted input. Page 126 DATASHEET GPIO RUNTIME DATA REGISTER REGISTER 1 BIT NO. OFFSET (HEX 7:5 DESCRIPTION SMSC LPC47M172 ...
Page 127
... When the GPIO is programmed as an output, the pin is excluded from the PME logic. HOST OPERATION READ LATCHED VALUE OF GPIO PIN WRITE NO EFFECT SMSC LPC47M172 GPIO Configuration Register bit-1 (Polarity Figure 7 ...
Page 128
... Datasheet 7.27.5 GPIO PME Functionality The LPC47M172 provides 12 GPIOs that can directly generate a PME. See the Table 7.16. The polarity bit in the GPIO control registers select the edge on these GPIO pins that will set the associated status bit in the PME_STS2 and PME_STS3 registers. The default is the low-to-high edge. If the corresponding enable bit in the PME_EN2 and PME_EN3 registers and the PME_EN bit in the PME_EN register is set, a PME will be generated ...
Page 129
... See the “Keyboard and Mouse PME Generation” section for information about using the keyboard and mouse signals to generate a PME. In the LPC47M172 the nIO_PME pin can be programmed open drain, active low, driver. The LPC47M172 nIO_PME pin is fully isolated from other external devices that might pull the nIO_PME signal low ...
Page 130
... These signals, as well as the Fan Tachometer registers, are described below. SMSC/Non-SMSC Register Sets (Rev. 02-27-04) FUNCTION Data bit 2 Data bit 3 Data bit 4 Data bit 5 Data bit 6 Data bit 7 (most significant bit) Parity bit (odd parity) Stop Bit (always 1) Page 130 DATASHEET SMSC LPC47M172 ...
Page 131
... The fan failure bit in the interrupt status register is set in the event of a stalled fan. Note: the fan tachometer reading register, which holds the count value, does not roll over – it stays at FFFFh in the SMSC LPC47M172 Advanced I/O Controller with Motherboard GLUE Logic ...
Page 132
... Open-Drain Output ISPU_400 VCC IDE Secondary Drive Active Input ISPU_400 VCC IDE Primary Drive Active Input Table 7.21 - nHD_LED Truth Table NSCSI Page 132 DATASHEET DESCRIPTION OUTPUT nHD_LED NOTES 0 LED On 0 LED On 0 LED On Hi-Z LED Off SMSC LPC47M172 ...
Page 133
... The green and yellow LED outputs are powered by VTR. INPUTS nSLP_S5 GRN_YLW Bit SMSC LPC47M172 Advanced I/O Controller with Motherboard GLUE Logic VCC 220 ohms RED nHD_LED Figure 7.6 - NHD_LED Circuit Table 7.22 - LED Pins POWER BUFFER DESCRIPTION WELL OD24 VTR Green Power LED Open-Drain Output ...
Page 134
... VTR 220 ohms GRN_LED YLW_LED Green Figure 7.7 - YLW_LED/GRN_LED Circuit Table 7.24 - Reference Generation Pins MAX OUT POWER CURRENT WELL 3.3mA VCC 3.3mA VTR Page 134 DATASHEET OUTPUTS GRN_LED YLW_LED 0. Hi-Z*** 0 220 ohms Yellow DESCRIPTION 5V Reference Output Highest System Standby Voltage SMSC LPC47M172 ...
Page 135
... V_5P0_STBY (through an external pull-up resistor), whichever is greater in amplitude. REF5V_STBY becomes a high impedance input while tracking the V_5P0_STBY power supply. REF5V_STBY is powered by VTR when VTR > V_5P0_STBY. STANDBY SUPPLY V_5P0_STBY < VTR V_5P0_STBY > VTR SMSC LPC47M172 Table 7.25 - REF5V MAIN SUPPLY REF5V VCC5V < VCC VCC VCC5V > ...
Page 136
... The nPCIRST_OUT and nPCIRST_OUT2 signals will be low when VCC=0. SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Backdrive Protection SMSC I/O Figure 7.9 - REF5V_STBY Table 7.27 - nIDE_RSTDRV Pin POWER BUFFER DESCRIPTION WELL OD8 VCC IDE Reset Output Table 7.28 - nIDE_RSTDRV Truth Table nIDE_RSTDRV (Output Page 136 DATASHEET V_5P0_STBY 1k 0 Hi-Z SMSC LPC47M172 ...
Page 137
... The DDC data pins and the DDC clock pins function as inputs shorted together through the isolation resistor. The DDC signals require external pull-up resistors on LPC47M172. See the “Pins That Require External Resistors” section for resistor values. See Figure 7.10 for recommended schematic implementation ...
Page 138
... Don’t Care No Current flow (0 mA) Current flows from DDCSDA_5V or 0V DDCSDA_3V 5.5V (max) No Current flow (0 mA) DDCSCL_5V CURRENT ACROSS THE SWITCH Don’t Care No Current flow (0 mA) Current flows from DDCSCL_5V or 0V DDCSCL_3V 5.5V (max) No Current flow (0 mA) Page 138 DATASHEET SMSC LPC47M172 ...
Page 139
... The SMB data pins and the SMB clock pins function as inputs shorted together through the isolation resistor when the switch is closed. The SMBus signals require external pull-up resistors on LPC47M172. See Figure 7.11 for recommended schematic implementation. The switch is controlled by the PWRGD_PS signal. The switch is closed as long as PWRGD_PS is ‘1’. The current flow is controlled by the external signals on the SMB pins ...
Page 140
... Figure 7.11 - SMBUS Isolation Circuit Page 140 DATASHEET CURRENT ACROSS THE SWITCH No Current flow (0 mA) Current flows from SMB_CLK_R or SMB_CLK_M No Current flow (0 mA) CURRENT DIRECTION ACROSS THE SWITCH No Current flow (0 mA) Current flows from SMB_DAT_R or SMB_DAT_M No Current flow (0 mA) VTR 2.7k 2.7k ICH, PCI SMSC LPC47M172 ...
Page 141
... The nFPRST is debounced internally. nFPRST has internal debounce circuitry that is valid on both edges for at least 16ms before the output is changed. The 32.768kHz is used to meet the timing requirement. See Figure 7.14 for nFPRST debounce timing. SMSC LPC47M172 Advanced I/O Controller with Motherboard GLUE Logic POWER BUFFER ...
Page 142
... The following figure shows the discrete implementation for the creation of the PWRGD_3V signal on the motherboard. nFPRST PWRGD_PS Figure 7.12 - PWRGD_3V Circuit, Discrete Implementation (SHOWING NFPRST INPUT DEBOUNCE CIRCUITRY) The following figure represents the integration of the logic into the LPC47M172. PWRGD_PS Figure 7.13 - PWRGD_3V Circuit in LPC47M172 SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Table 7.40 - PWRGD_3V Truth Table INPUTS ...
Page 143
... This circuit is used for glitch protection on the SCK line when moving in to and out of the S3 power state. This signal is only required for designs utilizing Rambus memory. This output functions according to the table below. See the figure below for the circuit implementation. PWRGD_3V (INPUT) SMSC LPC47M172 Release 15.8msec min Figure 7 ...
Page 144
... SMSC/Non-SMSC Register Sets (Rev. 02-27-04) RMB_SCK V_5P0_STBY 1k SCK_BJT_GATE Figure 7.15 - SCK_BJT_Gate Circuit Buffer Power Well OD8 VTR Open-Drain Output used for STR Circuitry OP14 VTR Latched Backfeed Cut Output for STR Circuitry INPUTS NSLP_S3 nBACKFEED_CUT Page 144 DATASHEET Description OUTPUT Hi-Z Hi-Z Hi-Z 0 SMSC LPC47M172 ...
Page 145
... The LATCHED_BF_CUT signal stays low and never turns on. The nSLP_S5 goes to its high value when the power rails have stabilized, approximately 25msec after power on. nBACKEED_CUT is pulled low a period t1 after nSLP_S5 goes high. The period t1 can be as short as 1msec. Typical measured values are SMSC LPC47M172 +5VTR 1k ...
Page 146
... Advanced I/O Controller with Motherboard GLUE Logic Datasheet approximately 200msec. The t1 and t2 values are guaranteed by the inherent design of the system and are not controlled by the LPC47M172. V_5P0_STBY nSLP_S3 PWRGD_PS nBACKFEED_CUT nSLP_S5 LATCHED_BF_CUT Figure 7.17 - Latched Backfeed Cut Power Up Sequence Table 7.46 - Latched Backfeed Cut Power Up Sequence Timing ...
Page 147
... LATCHED_BF_CUT low to high propagation delay. Measured from nBACKFEED_CUT/nSLP_S5 threshold to 10% of LATCHED_BF_CUT CO Output Capacitance CL Load Capacitance t3 nBACKFEED_CUT inactive to nSLP_S5 active t4 nSLP_S5 inactive to nBACKFEED_CUT active SMSC LPC47M172 signal goes high when nBACKFEED_CUT t3 Tpropf Tf MIN 30 1 Page 147 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic ...
Page 148
... Figure 7.20 - Latched Backfeed Cut Flowchart SMSC/Non-SMSC Register Sets (Rev. 02-27-04) nBACKFEED_CUT = 1? No Yes LATCHED_BF_CUT = 1 (After Tpropr) nSLP_S5 = nBACKFEED_CUT = 0? Yes LATCHED_BF_CUT = 0 (After Tpropf) Page 148 DATASHEET Yes LATCHED_BF_CUT = 0 (After Tpropf) (This is end of T3) nSLP_S5 = 1? No Yes Period T4 nBACKFEED_CUT = 0 (Controlled by nSLP_S3 and PWRGD_PS) SMSC LPC47M172 ...
Page 149
... The polarity bit will affect the output and input to the CNR logic. The output type select bit will also affect the GP24 pin. If GP24 is programmed as GPIO input, it will not affect the nCDC_DWN_ENAB input into the CNR logic. It will function as a normal GPIO input and can be used as a PME event. SMSC LPC47M172 Table 7.48 - nRSMRST Pin POWER BUFFER ...
Page 150
... This follows the boolean equation: (nAUD_LNK_RST)x( nCDC_DWN_ENAB )=nCDC_DWN_RST nAUD_LNK_RST See Table 13.6 for CNR timing. SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Table 7.50 - CNR Logic Truth Table INPUTS NCDC_DWN_ENAB (NOTE SMSC I/O 10k Powered by VTR (3.3V) Figure 7.21 - CNR Circuit Page 150 DATASHEET OUTPUT nCDC_DWN_RST nCDC_DWN_RST SMSC LPC47M172 ...
Page 151
... R/W 0x01 R/W 0xFF 1C R/W 0xFF 1E- SMSC LPC47M172 Advanced I/O Controller with Motherboard GLUE Logic SOFT VCC POR VTR POR RESET - 0x00 - - - - - 0x00 - - - - - 0x00 - - 0x00 - - 0x00 - - - - - 0x00 - - 0x00 - - 0x00 - - - - - 0x03 - - 0x00 - - 0x00 - - 0x00 - - ...
Page 152
... DESCRIPTION (Type) 0x00 Bit[0] PME_Status = 0 (default) (R/ Set when LPC47M172 would normally assert the nIO_PME signal, independent of the state of the PME_En bit. Bit[7:1] Reserved PME_Status is not affected by Vcc POR, SOFT RESET or HARD RESET. Writing a “1” to PME_Status will clear it and cause the LPC47M172 to stop asserting nIO_PME, in enabled. Writing a “ ...
Page 153
... Bits[7:0] Reserved – reads return 0 (R) 0x0C PME Wake Status Register 3 This register is used to enable individual LPC47M172 (R/W) PME wake sources onto the nIO_PME wake bus. When the PME Wake Enable register bit for a wake source is active (“1”), if the source asserts a wake event so that the associated status bit is “ ...
Page 154
... SMSC/Non-SMSC Register Sets (Rev. 02-27-04) DESCRIPTION (Type) 0x0D PME Wake Enable Register 2 This register is used to enable individual LPC47M172 (R/W) PME wake sources onto the nIO_PME wake bus. When the PME Wake Enable register bit for a wake source is active (“1”), if the source asserts a wake event so that the associated status bit is “ ...
Page 155
... Tach2 LSB Default = 0x00 on VTR POR Tach2 MSB Default = 0x00 on VTR POR nIO_PME Register Default = 0x80 on VTR POR MSC_STS Default = 0x00 on VTR POR SMSC LPC47M172 DESCRIPTION (Type) 0x11 Keyboard Scan Code Bit[0] LSB of Scan Code (R/ Bit[7] MSB of Scan Code 0x12 This register is least significant 8-bit of the 16-bit Fan Tachometer 1 reading ...
Page 156
... Interrupt frame driven low in the SER (R/W) IRQ stream. This must be enabled through the INT_G Configuration Register. Bit[0] Reserved Bit[1] nINT1 Bit[2] nINT2 Bit[3] nINT3 Bit[4] nINT4 Bit[5] nINT5 Bit[6] nINT6 Bit[7] nINT7 Note: To enable/disable this register see Logical Device A (0xF1) Page 156 DATASHEET SMSC LPC47M172 ...
Page 157
... Producing an interrupt in the SER_IRQ stream by setting these bits to “0” overrides other interrupt sources for the SER_IRQ stream. No other functional logic in the LPC47M172 sets bits in the register. These bits are only cleared by writing “1” to the bit location. ...
Page 158
... Page 158 DATASHEET REGISTER GP10 GP11 GP12 GP13 GP14 GP15 GP16 GP17 GP20 GP21 GP22 GP23 GP24 Reserved – reads return 0 GP1 GP2 Reserved – reads return 0 SMSC LPC47M172 ...
Page 159
... VTR POR GP14 Default = 0x01 on VTR POR GP15 Default = 0x01 on VTR POR GP16 Default = 0x01 on VTR POR SMSC LPC47M172 DESCRIPTION (Type) 0x00 General Purpose I/O bit 1.0 Bit[0] In/Out : =1 Input, =0 Output (R/W) Bit[1] Polarity : =1 Invert Invert Bits[6:2] Reserved Bit[7] Output Type Select 1=Open Drain ...
Page 160
... Bit[7] Output Type Select 1=Open Drain 0=Push Pull 0x0B General Purpose I/O bit 2.3 Bit[0] In/Out : =1 Input, =0 Output (R/W) Bit[1] Polarity : =1 Invert Invert Bit[2] Alternate Function Select 1=DDCSCL_3V 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull Page 160 DATASHEET SMSC LPC47M172 ...
Page 161
... The In/Out, Polarity and Output Type Select Bits do not apply when DDCSCL/DDCSDA signals are selected. Note 2: If the EETI function is selected for this GPIO then both a high-to-low and low-to-high edge will set the PME and MSC status bits. SMSC LPC47M172 DESCRIPTION (Type) 0x0C General Purpose I/O bit 2.4 ...
Page 162
... Tach1 MSB Tach2 LSB Tach2 MSB nIO_PME Register MSC_STS Force Disk Change Floppy Data Rate Select Shadow UART1 FIFO Control Shadow Interrupt Generating Register 1 Interrupt Generating Register 2 UART2 FIFO Control Shadow Reserved – reads return 0 GP10 GP11 GP12 GP13 GP14 SMSC LPC47M172 ...
Page 163
... PME_En bit. Bit[7:1] Reserved PME_Status is not affected by Vcc POR, SOFT RESET or HARD RESET. Writing a “1” to PME_Status will clear it and cause the LPC47M172 to stop asserting nIO_PME, in enabled. Writing a “0” to PME_Status has no effect. Bits[7:0] Reserved – reads return 0 ...
Page 164
... Bit[5] GP15 Bit[6] GP16 Bit[7] GP17 The PME Wake Status register is not affected by Vcc POR, SOFT RESET or HARD RESET. Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME Wake Status Register has no effect. Page 164 DATASHEET SMSC LPC47M172 ...
Page 165
... PME status bit will be cleared. Bits[7:0] Reserved – reads return 0 PME Wake Status Register 3 This register is used to enable individual LPC47M172 PME wake sources onto the nIO_PME wake bus. When the PME Wake Enable register bit for a wake source is active (“1”), if the source asserts a wake event so that the associated status bit is “ ...
Page 166
... SMSC/Non-SMSC Register Sets (Rev. 02-27-04) DESCRIPTION PME Wake Enable Register 2 This register is used to enable individual LPC47M172 PME wake sources onto the nIO_PME wake bus. When the PME Wake Enable register bit for a wake source is active (“1”), if the source asserts a wake event so that the associated status bit is “1” ...
Page 167
... Default = 0x00 on (R) VTR POR nIO_PME Register 0x16 Default = 0x80 on (R/W) VTR POR SMSC LPC47M172 Advanced I/O Controller with Motherboard GLUE Logic DESCRIPTION LED Register Bit[0] GRN_YLW 0 = Select YLW_LED if nSLP_S5 if high 1 = Select GRN_LED if nSLP_S5 is high Bit[1] SDY_BLK 0 = Blink at 0.67 Hz with 39.6% duty cycle (0.59375 sec high, 0.90625 low) ...
Page 168
... Bit[5] Reserved Bit[6] Power Down Bit[7] Soft Reset UART FIFO Control Shadow 1 Bit[0] FIFO Enable Bit[1] RCVR FIFO Reset Bit[2] XMIT FIFO Reset Bit[3] DMA Mode Select Bit[5:4] Reserved Bit[6] RCVR Trigger (LSB) Bit[7] RCVR Trigger (MSB) Page 168 DATASHEET SMSC LPC47M172 ...
Page 169
... GP10 0x20 Default = 0x01 (R/W) on VTR POR SMSC LPC47M172 Advanced I/O Controller with Motherboard GLUE Logic DESCRIPTION Interrupt Generating Register 1 (Note 2) 0=Corresponding Interrupt frame driven low in the SER IRQ stream. This must be enabled through the INT_G Configuration Register. Bit[0] Reserved Bit[1] nINT1 ...
Page 170
... Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/O bit 1.6 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert Invert Bit[2] Alternate Function Select 1=FAN_TACH1 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull Page 170 DATASHEET SMSC LPC47M172 ...
Page 171
... Default = 0x04 (R/W) on VTR POR Note 3 GP22 0x2A Default = 0x04 (R/W) on VTR POR Note 3 SMSC LPC47M172 Advanced I/O Controller with Motherboard GLUE Logic DESCRIPTION General Purpose I/0 bit 1.7 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity :=1 Invert Invert Bit[2] Alternate Function Select 1=FAN_TACH2 0=GPIO Bits[6:3] Reserved ...
Page 172
... Bit[0] GP10 Bit[1] GP11 Bit[2] GP12 Bit[3] GP13 Bit[4] GP14 Bit[5] GP15 Bit[6] GP16 Bit[7] GP17 General Purpose I/O Data Register 2 Bit[0] GP20 Bit[1] GP21 Bit[2] GP22 Bit[3] GP23 Bit[4] GP24 Bits[7:5] Reserved Bits[7:0] Reserved – reads return 0 Page 172 DATASHEET SMSC LPC47M172 ...
Page 173
... System Elements 11.1.1 Primary Configuration Address Decoder After a hard reset (nPCI_RESET pin asserted) or Vcc Power On Reset the LPC47M172 is in the Run Mode with all logical devices disabled. The logical devices may be configured through two standard Configuration I/O Ports (INDEX and DATA) by placing the LPC47M172 into Configuration Mode. ...
Page 174
... To exit the Configuration State the system writes 0xAA to the CONFIG PORT. The chip returns to the RUN State. Note : Only two states are defined (Run and Configuration). In the Run State the chip will always be ready to enter the Configuration State. SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 174 DATASHEET SMSC LPC47M172 ...
Page 175
... LD_NUM Bit The LD_NUM bit in the TEST 7 global configuration register (0x29) is used to select between the logical device numbering in the LPC47M172. LD_NUM is determined by the state of pin 117 as described in Chapter 2. See the TEST 7 register for LD_NUM bit description. Table 11.1 and Table 11.2 summarize the logical device registers when LD_NUM bit is 0 and 1. ...
Page 176
... Advanced I/O Controller with Motherboard GLUE Logic Datasheet Table 11.1 - LPC47M172 Configuration Registers Summary, LD_NUM bit = 0 INDEX TYPE PCI RESET 0x02 W 0x00 0x03 R - 0x07 R/W 0x00 0x20 R 0x14 0x21 R 0x04 0x22 R/W 0x00 0x23 R - 0x24 R/W 0x44 0x2E 0x26 R/W 0x00 0x27 R/W 0x28 R/W - 0x29 R/W 0x00 0x2A R/W - 0x2B ...
Page 177
... R/W 0x00 0x60 R/W 0x00 0x61 R/W Note : Reserved registers are read-only, reads return 0. Note 1: Bits[7:5] of this register reset on VTR POR only. SMSC LPC47M172 Advanced I/O Controller with Motherboard GLUE Logic SOFT VCC POR VTR POR RESET 0x08 0x08 - 0x00 0x00 0x00 0x00 ...
Page 178
... Advanced I/O Controller with Motherboard GLUE Logic Datasheet Table 11.2 - LPC47M172 Configuration Register Summary, LD_NUM=1 INDEX TYPE PCI RESET 0x02 W 0x00 0x03 R - 0x07 R/W 0x00 0x20 R 0x14 0x21 R 0x04 0x22 R/W 0x00 0x23 R - 0x24 R/W 0x44 0x26 R/W 0x2E 0x27 R/W 0x00 0x28 R/W - 0x29 R/W 0x01 0x2A R/W - 0x2B R/W - 0x2C ...
Page 179
... LOGICAL DEVICE B CONFIGURATION REGISTERS (Reserved) LOGICAL DEVICE C CONFIGURATION REGISTERS (Reserved) Note: Reserved registers are read-only, reads return 0. Note 1: Bits[7:6, 5 and 1] of KRESET and GateA20 Select register reset on VTR POR only. SMSC LPC47M172 Advanced I/O Controller with Motherboard GLUE Logic SOFT VCC POR VTR POR RESET ...
Page 180
... Reserved - Writes are ignored, reads return 0 . CHIP LEVEL, SMSC DEFINED 0x20 R A read only register which provides device identification. Bits[7:0] = 0x14 when read. 0x21 R A read only register which provides device revision information. Bits[7:0] = current revision when read. Page 180 DATASHEET SMSC LPC47M172 ...
Page 181
... Configuration Address Byte 1 Default = 0x00 on VCC POR and HARD RESET TEST 8 Default = 0x00 on VCC POR and VTR POR SMSC LPC47M172 ADDRESS DESCRIPTION CHIP (GLOBAL) CONTROL REGISTERS 0x22 R/W Bit[0] FDC Power Bit[1] Reserved Bit[2] Reserved Bit[3] Parallel Port Power Bit[4] Serial Port 1 Power ...
Page 182
... R/W Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results. 0x2E R/W Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results. Page 182 DATASHEET SMSC LPC47M172 ...
Page 183
... VCC POR, VTR POR, HARD RESET and SOFT RESET Logical Device Control Logical Device Control Memory Base Address SMSC LPC47M172 ADDRESS DESCRIPTION CHIP (GLOBAL) CONTROL REGISTERS 0x2F R/W Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results. ...
Page 184
... Reserved - not implemented. These register locations ignore writes and return zero when read. (0xE0-0xFE) Reserved – Vendor Defined (see SMSC defined Logical Device Configuration Registers). 0xFF Reserved Page 184 DATASHEET SMSC LPC47M172 ...
Page 185
... Notes: A DMA channel is activated by setting the DMA Channel Select register to [0x01-0x03] AND : - For the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register. SMSC LPC47M172 Advanced I/O Controller with Motherboard GLUE Logic DEFINITION Bits[3:0] selects which interrupt is used for the primary Interrupt ...
Page 186
... D. Keyboard Controller: Refer to the KBD section of this spec. SMSC/Non-SMSC Register Sets (Rev. 02-27-04) IRQ CONTROLLED BY PRINTER IRQE SPP IRQE FIFO (on) ECP (on) EPP IRQE RES IRQE TEST (on) CONFIG IRQE Page 186 DATASHEET DMA CONTROLLED BY dmaEn dmaEn dmaEn dmaEn dmaEn dmaEn dmaEn dmaEn SMSC LPC47M172 ...
Page 187
... Serial Port 0x60,0x61 0x04 Power Control 0x60,0x61 0x05 Mouse n/a 0x06 KYBD n/a 0x07 GPIO 0x60,0x61 SMSC LPC47M172 Advanced I/O Controller with Motherboard GLUE Logic BASE I/O RANGE (NOTE 1) [0x0100:0x0FF8 SRA +1 : SRB ON 8 BYTE BOUNDARIES +2 : DOR +3 : TSR +4 : MSR/DSR +5 : FIFO +7 : DIR/CCR [0x0100:0x0FFC Data/ecpAfifo ON 4 BYTE BOUNDARIES ...
Page 188
... ON 8 BYTE BOUNDARIES +402h : ecr (all modes supported EPP Address EPP is only available when +4 : EPP Data 0 the base address EPP Data 1 byte boundary EPP Data EPP Data 3 Page 188 DATASHEET FIXED BASE OFFSETS FIXED BASE OFFSETS SMSC LPC47M172 ...
Page 189
... This chip uses address bits [A11:A0] to decode the base address of each of its logical devices. Bit 6 of the OSC Global Configuration Register (CR24) must be set to ‘1’ and Address Bits [A15:A12] must be ‘0’ for 16 bit address qualification. SMSC LPC47M172 Advanced I/O Controller with Motherboard GLUE Logic BASE I/O ...
Page 190
... AND Forced Write Protect) OR (nDS1 AND Forced Write Protect) OR nWRTPRT (from the FDD Interface) Bit[1] Reserved Bits[3:2] Density Select = 00 Normal (default Normal (reserved for users (forced to logic “1” (forced to logic “0”) Bit[7:4] Reserved. Page 190 DATASHEET DEFINITION SMSC LPC47M172 ...
Page 191
... REG INDEX Serial Port 2 Mode Register Default = 0x00 on VCC POR, VTR POR and HARD RESET SMSC LPC47M172 0xF2 R/W Bits[1:0] Floppy Drive A Type Bits[3:2] Reserved (could be used to store Floppy Drive B type) Bits[5:4] Reserved (could be used to store Floppy Drive C type) Bits[7:6] Reserved (could be used to store Floppy Drive ...
Page 192
... Standard & Bi-directional Mode (000 Pulsed Low, released to high- IRQ follows nACK when parallel port in EPP Mode or [Printer,SPP, EPP] under ECP. IRQ level type when the parallel port is in ECP, TEST, or Centronics FIFO Mode. Page 192 DATASHEET DEFINITION SMSC LPC47M172 ...
Page 193
... Set the share IRQ bit. Note: If both UARTs are configured to use different IRQs and the share IRQ bit is set, then both of the UART IRQs will assert when either UART generates an interrupt. SMSC LPC47M172 0xF1 R/W Bits[3:0] Reserved. Set to zero Bit [4] TIMEOUT_SELECT = 0 TMOUT (EPP Status Reg.) cleared on write of ‘1’ to TMOUT ...
Page 194
... It will disable the 32kHz clock input to the logic when turned off. The logic will draw no power when disabled. 0= “Wake on specific key” logic is on (default) 1= “Wake on specific key” logic is off Bits[7:2] are reserved Page 194 DATASHEET SMSC LPC47M172 ...
Page 195
... NAME REG INDEX INT_G Default = 0x00 on VCC POR, VTR POR, HARD RESET and SOFT RESET SMSC LPC47M172 DEFINITION 0xF1 Bit[7:1] Reserved R/W Bit[0] INT_G Enable 0 = Disable Interrupt Generating Registers (INT_GENx) from affecting the serial IRQ stream 1 = Enable Interrupt Generating Registers to drive one or more frames low in the ...
Page 196
... SMSC/Non-SMSC Register Sets (Rev. 02-27-04) MIN TYP MAX V 0 2 2 2.2 5.5 IH 250 HYS Page 196 DATASHEET + +150 C UNITS COMMENTS V TTL Levels V TTL Levels V TTL Levels V TTL Levels uA V Schmitt Trigger V Schmitt Trigger mV SMSC LPC47M172 ...
Page 197
... Low Output Level High Output Level V For REF5V_STBY Low Output Level High Output Level V O8 Output Buffer Low Output Level High Output Level V OD8 Output Buffer Low Output Level High Output Level V SMSC LPC47M172 MIN TYP MAX V 0 2.2 5.5 IH 400 HYS V 0.8 ...
Page 198
... OL 2.4 OH Page 198 DATASHEET UNITS COMMENTS 12mA -6mA 12mA OL V Open-Drain 14mA -14mA 24mA OL V Open-Drain V TTL Levels V TTL Levels 8mA -4mA OH V Schmitt Trigger V Schmitt Trigger 8mA -4mA OH SMSC LPC47M172 ...
Page 199
... High Output Level V IO_SW Input/Output Special Pins of this type are connected in pairs through a switch. The switch provides a 25 Type ohm (max) resistance to ground when closed. See SMBus Isolation Circuitry and Voltage Translation Circuit sections for a description. Note: SMSC LPC47M172 MIN TYP MAX V 0 ...
Page 200
... Page 200 DATASHEET UNITS COMMENTS V TTL Levels V TTL Levels 24mA OL V Open-Drain Vcc Vcc Vcc and 3.3V CC µ 3.6V Max IN µ µ 5.5V Max IN µ SMSC LPC47M172 ...