SAB80C517-M16 SIEMENS [Siemens Semiconductor Group], SAB80C517-M16 Datasheet - Page 163

• Manufacturer Part Number: SAB80C517-M16
• Description: 8-Bit CMOS Single-Chip Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Figure 8-10
Priority-Within-Level Structure.
High
IE0
TF0
IE1
TF1
RI0 + TI0
TF2 + EXF2
Note:
This "priority-within-level" structure is only used to resolve simultaneous requests of the same
priority level.
8.3
The interrupt flags are sampled at S5P2 in each machine cycle. The sampled flags are polled during
the following machine cycle. lf one of the flags was in a set condition at S5P2 of the preceding cycle,
the polling cycle will find it and the interrupt system will generate a LCALL to the appropriate service
routine, provided this hardware-generated LCALL is not blocked by any of the following conditions:
1)
2)
3)
Any of these three conditions will block the generation of the LCALL to the interrupt service routine.
Condition 2 ensures that the instruction in progress is completed before vectoring to any service
routine. Condition 3 ensures that if the instruction in progress is RETI or any write access to
registers IEN0, IEN1, IEN2 or IP0 and IP1, then at least one more instruction will be executed before
any interrupt is vectored too; this delay guarantees that changes of the interrupt status can be
observed by the CPU.
Semiconductor Group
An interrupt of equal or higher priority is already in progress.
The current (polling) cycle is not in the final cycle of the instruction in progress.
The instruction in progress is RETI or any write access to registers IEN0, IEN1, IEN2 or IP0
and IP1.
How Interrupts are Handled
Interrupt Source
RI1+TI1
CTF
–
–
IADC
IEX2
IEX3
IEX4
IEX5
IEX6
Low
164
Priority
High
Low
Interrupt System