SAB80C517-M16 SIEMENS [Siemens Semiconductor Group], SAB80C517-M16 Datasheet - Page 130

• Manufacturer Part Number: SAB80C517-M16
• Description: 8-Bit CMOS Single-Chip Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

On-Chip Peripheral Components
Normalizing
Normalizing is done on an integer variable stored in MD0 (least significant byte) to MD3 (most
significant byte). This feature is mainly meant to support applications where floating point arithmetic
is used. "To normalize" means, that all reading zeroes of an integer variable in registers MD0 to
MD3 are removed by shift left operations. The whole operation is completed when the MSB (most
significant bit) contains a ’1’.
To select a normalize operation, the five bit field ARCON.0 to ARCON.4 must be cleared. That
means, a write-to-ARCON instruction with the value XXX0 0000 B starts the operation.
After normalizing, bits ARCON.0 to ARCON.4 contain the number of shift left operations which were
done. This number may further on be used as an exponent. The maximum number of shifts in a
normalize operation is 31 ( = 2
5
– 1). The operation takes six machine cycles at most, that means
6 microseconds at 12 MHz.
Shifting
In the same way - by a write-to-ARCON instruction - a shift left/right operation can be started. In this
case register bit SLR (ARCON.5) has to contain the shift direction, and ARCON.0 to ARCON.4 the
shift count (which must not be 0, otherwise a normalize operation would be executed). During shift,
zeroes come into the left or right end of the registers MD0 or MD3, respectively.
The first machine cycle of a shift left/right operation executes four shifts, while all following cycles
perform 6 shifts. Hence, a 31-bit shift takes 6 microseconds at 12 MHz.
Completion of both operations, normalize and shift, can also be controlled by the error flag
mechanism described in 7.6.4. The error flag is set if one of the relevant registers (MD0 through
MD3) is accessed before the previously commenced operation has been completed.
For proper operation of the error flag mechanism, it is necessary to take care that the right write or
read sequence to or from registers MD0 to MD3 (see table 7-12) is maintained.
Semiconductor Group
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