PEB2466 SIEMENS [Siemens Semiconductor Group], PEB2466 Datasheet - Page 47

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PEB2466

Manufacturer Part Number
PEB2466
Description
Four Channel Codec Filter with PCM- and m-Controller Interface SICOFI4-mC
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet

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3.5.7
This register configures the operation of the PCM-interface
C-MODE
X-S
R-S
DRV_0
Shift
PCM-OFFSET
Semiconductor Group
Bit 7
C-MODE
XR6 Extended Register 6
Defines the CLK-Mode for the PCM-interface
C-Mode = 0:
C-Mode = 1:
Transmit Slope
X-S = 0:
X-S = 1:
Receive Slope
R-S= 0:
R-S= 1:
Driving Mode for Bit 0 (only available with single clocking mode)
DRV_0 = 0:
DRV_0 = 1:
Shifts the access to DXA/B and DRA/B for one PCLK-period
(only available with double clocking mode)
Shift = 0:
Shift = 1:
Offset in number of data-clock periods added to Time slot
0 0 0:
0 0 1:
...
1 1 1
X-S
R-S
Single clocking is used
Double clocking is used
Transmission starts with rising edge
Transmission starts with falling edge
Data is sampled with falling edge of PCLK
Data is sampled with rising edge of PCLK
Bit 0 is driven the whole PCLK-period
Bit 0 is driven during the first half of the
PCLK-period only
No shift takes place
Access to DXA/B and DRA/B is shifted for one
PCLK-per.
No offset is added
One data clock period is added
Seven data clock periods are added
DRV_0
47
Shift
Programming the SICOFI
PCM-OFFSET
PEB 2466
0
®
-4- C
02.97

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