PEB2466 SIEMENS [Siemens Semiconductor Group], PEB2466 Datasheet - Page 18

no-image

PEB2466

Manufacturer Part Number
PEB2466
Description
Four Channel Codec Filter with PCM- and m-Controller Interface SICOFI4-mC
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PEB2466H
Manufacturer:
TEMIC
Quantity:
115 183
Part Number:
PEB2466H
Manufacturer:
INFINEON
Quantity:
672
Part Number:
PEB2466H V1.4
Manufacturer:
Infineon
Quantity:
1 045
Part Number:
PEB2466H V2.2
Manufacturer:
Infineon
Quantity:
885
Part Number:
PEB2466H V2.2
Manufacturer:
INFINEON/英飞凌
Quantity:
20 000
Part Number:
PEB2466HV1.2
Manufacturer:
SIEMENS
Quantity:
10 927
Company:
Part Number:
PEB2466HV1.2
Quantity:
125
Part Number:
PEB2466HV1.3
Manufacturer:
INFINEON/英飞凌
Quantity:
20 000
Part Number:
PEB2466HV2.2
Manufacturer:
INFINEON/英飞凌
Quantity:
20 000
Semiconductor Group
2.2
Two serial PCM-interfaces are used for the transfer of A- or -law compressed voice
data. The PCM-interface consist of 8 pins:
PCLK:
FSC:
DRA:
DRB:
DXA:
DXB:
TCA:
TCB:
The Frame Sync FSC pulse identifies the beginning of a receive and transmit frame for
all of the four channels. The PCLK clock is the signal to synchronize the data transfer on
both lines DXA (DXB) and DRA (DRB). Bytes in all channels are serialized to 8 bit width
and MSB first. As a default setting, the rising edge indicates the start of the bit, while the
falling edge is used to latch the contents of the received data on DRA (DRB). If the
double clock rate is chosen (twice the transmission rate) the first rising edge indicates
the start of a bit, while the second falling edge is used for latching the contents of the
data line DRA (DRB) by default.
The data rate of the interface can vary from 2 128 kbit/s to 2 8192 kbit/s (2 highways)
A frame may consist of up to 128 time slots of 8 bits each. In the Time Slot Configuration
Registers CR5 and CR6 the user can select an individual time slot, and an individual
PCM-highway, for any of the four voice channels. Receive and transmit time slots can
also be programmed individually. An extra delay of up to 7 clocks, valid for all channels,
as well as the sampling slope may be programmed (see XR6).
When the SICOFI-4- C is transmitting data on DXA (DXB), pin TCA (TCB) is activated
to control an extra external driving device.
The PCM-interface
PCM-Clock, 128 kHz to 8192 kHz
Frame Synchronization Clock, 8 kHz
Receive Data input for PCM-highway A
Receive Data input for PCM-highway B
Transmit Data output for PCM-highway A
Transmit Data output for PCM-highway B
Transmit Control Output for PCM-highway A, active low during transmission
Transmit Control Output for PCM-highway B, active low during transmission
18
Functional Description
PEB 2466
02.97

Related parts for PEB2466