LAN9221i SMSC [SMSC Corporation], LAN9221i Datasheet - Page 98

• Manufacturer Part Number: LAN9221i
• Description: High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
• Manufacturer: SMSC [SMSC Corporation]

Revision 2.6 (12-04-08)
5.3.16
5.3.17
31-16
BITS
BITS
15-0
31:0
Reserved
General Purpose Timer Current Count (GPT_CNT). This 16-bit field
reflects the current value of the GP Timer.
Word Swap. If this field is set to 00000000h, or anything except
0xFFFFFFFFh, the LAN9221/LAN9221i maps words with address bit A[1]=1
to the high order words of the CSRs and Data FIFOs, and words with
address bit A[1]=0 to the low order words of the CSRs and Data FIFOs. If
this field is set to 0xFFFFFFFFh, the LAN9221/LAN9221i maps words with
address bit A[1]=1 to the low order words of the CSRs and Data FIFOs, and
words with address bit A[1]=0 to the high order words of the CSRs and Data
FIFOs.
Note:
GPT_CNT-General Purpose Timer Current Count Register
This register reflects the current value of the GP Timer.
WORD_SWAP—Word Swap Control
This register controls how words from the host data bus are mapped to the CSRs and Data FIFOs
inside the LAN9221/LAN9221i. The LAN9221/LAN9221i always sends data from the Transmit Data
FIFO to the network so that the low order word is sent first, and always receives data from the network
to the Receive Data FIFO so that the low order word is received first.
Offset:
Offset:
Word swap is used in conjunction with the mixed endian
functionality to determine the final byte ordering. Refer to
3.7.3, "Mixed Endian Support"
DESCRIPTION
DESCRIPTION
90h
98h
DATASHEET
for more information.
98
High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Size:
Size:
Section
32 bits
32 bits
NASR
TYPE
TYPE
R/W
RO
RO
SMSC LAN9221/LAN9221i
00000000h
DEFAULT
DEFAULT
FFFFh
Datasheet
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