PIC18F2525 MICROCHIP [Microchip Technology], PIC18F2525 Datasheet - Page 297
![no-image](/images/no-image-200.jpg)
PIC18F2525
Manufacturer Part Number
PIC18F2525
Description
28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F2525.pdf
(390 pages)
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Quantity
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Company:
Part Number:
PIC18F2525-E/SP
Manufacturer:
Microchip Technology
Quantity:
135
Company:
Part Number:
PIC18F2525-I/SO
Manufacturer:
HITTITE
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101
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Part Number:
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Manufacturer:
SANYO
Quantity:
4 000
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NEGF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
2004 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
REG
Q1
=
=
register ‘f’
Negate f
NEGF
0
a
( f ) + 1
N, OV, C, DC, Z
Location ‘f’ is negated using two’s
complement. The result is placed in the
data memory location ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
NEGF
Read
0110
Q2
f
0011 1010 [3Ah]
1100 0110 [C6h]
[0,1]
255
f {,a}
REG, 1
f
110a
Process
Data
Q3
95 (5Fh). See
ffff
register ‘f’
PIC18F2525/2620/4525/4620
Write
Q4
ffff
Preliminary
NOP
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
None.
Q Cycle Activity:
Decode
Q1
operation
No Operation
NOP
None
No operation
None
No operation.
1
1
0000
1111
Q2
No
0000
xxxx
operation
Q3
No
DS39626B-page 295
0000
xxxx
operation
Q4
No
0000
xxxx
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