ENC28J60-C/ML MICROCHIP [Microchip Technology], ENC28J60-C/ML Datasheet - Page 37

• Manufacturer Part Number: ENC28J60-C/ML
• Description: Stand-Alone Ethernet Controller with SPI Interface
• Manufacturer: MICROCHIP [Microchip Technology]

REGISTER 6-2:
© 2006 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
PADCFG2
R/W-0
PADCFG2:PADCFG0: Automatic Pad and CRC Configuration bits
111 = All short frames will be zero padded to 64 bytes and a valid CRC will then be appended
110 = No automatic padding of short frames
101 = MAC will automatically detect VLAN Protocol frames which have a 8100h type field and auto-
100 = No automatic padding of short frames
011 = All short frames will be zero padded to 64 bytes and a valid CRC will then be appended
010 = No automatic padding of short frames
001 = All short frames will be zero padded to 60 bytes and a valid CRC will then be appended
000 = No automatic padding of short frames
TXCRCEN: Transmit CRC Enable bit
1 = MAC will apend a valid CRC to all frames transmitted regardless of PADCFG. TXCRCEN must be
0 = MAC will not append a CRC. The last 4 bytes will be checked and if it is an invalid CRC, it will be
PHDREN: Proprietary Header Enable bit
1 = Frames presented to the MAC contain a 4-byte proprietary header which will not be used when
0 = No proprietary header is present. The CRC will cover all data (normal operation).
HFRMEN: Huge Frame Enable bit
1 = Frames of any size will be allowed to be transmitted and receieved
0 = Frames bigger than MAMXFL will be aborted when transmitted or received
FRMLNEN: Frame Length Checking Enable bit
1 = The type/length field of transmitted and received frames will be checked. If it represents a length, the
0 = Frame lengths will not be compared with the type/length field
FULDPX: MAC Full-Duplex Enable bit
1 = MAC will operate in Full-Duplex mode. PDPXMD bit must also be set.
0 = MAC will operate in Half-Duplex mode. PDPXMD bit must also be clear.
PADCFG1
R/W-0
set if PADCFG specifies that a valid CRC will be appended.
reported in the transmit status vector.
calculating the CRC
frame size will be compared and mismatches will be reported in the transmit/receive status vector.
MACON3: MAC CONTROL REGISTER 3
matically pad to 64 bytes. If the frame is not a VLAN frame, it will be padded to 60 bytes. After
padding, a valid CRC will be appended.
W = Writable bit
‘1’ = Bit is set
PADCFG0
R/W-0
TXCRCEN
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PHDREN
R/W-0
HFRMEN
R/W-0
x = Bit is unknown
FRMLNEN
ENC28J60
R/W-0
DS39662B-page 35
FULDPX
R/W-0
bit 0