ENC28J60-C/ML MICROCHIP [Microchip Technology], ENC28J60-C/ML Datasheet - Page 13

• Manufacturer Part Number: ENC28J60-C/ML
• Description: Stand-Alone Ethernet Controller with SPI Interface
• Manufacturer: MICROCHIP [Microchip Technology]

3.0
All memory in the ENC28J60 is implemented as static
RAM. There are three types of memory in the
ENC28J60:
• Control Registers
• Ethernet Buffer
• PHY Registers
The Control registers’ memory contains the registers
that are used for configuration, control and status
retrieval of the ENC28J60. The Control registers are
directly read and written to by the SPI interface.
FIGURE 3-1:
© 2006 Microchip Technology Inc.
Note:
ECON1<1:0>
MEMORY ORGANIZATION
= 00
= 01
= 10
= 11
Memory areas are not shown to scale. The size of the control memory space has been scaled to show detail.
ENC28J60 MEMORY ORGANIZATION
Bank 0
Bank 1
Bank 2
Bank 3
1Ah
1Fh
1Ah
1Fh
1Ah
1Fh
1Fh
00h
19h
00h
19h
00h
19h
00h
19h
1Ah
Control Registers
Registers
Registers
Registers
Registers
Common
Common
Common
Common
Preliminary
Buffer Pointers in Bank 0
The Ethernet buffer contains transmit and receive
memory used by the Ethernet controller in a single
memory space. The sizes of the memory areas are
programmable by the host controller using the SPI
interface. The Ethernet buffer memory can only be
accessed via the read buffer memory and write buffer
memory SPI commands (see Section 4.2.2 “Read
Buffer Memory Command” and Section 4.2.4 “Write
Buffer Memory Command”).
The PHY registers are used for configuration, control
and status retrieval of the PHY module. The registers
are not directly accessible through the SPI interface;
they can only be accessed through Media Independent
Interface Management (MIIM) implemented in the
MAC.
Figure 3-1 shows the data memory organization for the
ENC28J60.
PHY Registers
Ethernet Buffer
ENC28J60
DS39662B-page 11
0000h
1FFFh
00h
1Fh