KM68257C-12 SAMSUNG [Samsung semiconductor], KM68257C-12 Datasheet - Page 8

• Manufacturer Part Number: KM68257C-12
• Description: 32Kx8 Bit High Speed Static RAM(5V Operating(, Evolutionary Pin out. Operated at Commercial Temperature Range.
• Manufacturer: SAMSUNG [Samsung semiconductor]

KM68257C/CL
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write ends at the ear-
3. t
4. t
5. t
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output mus t not
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycl e.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
DATA RETENTION CHARACTERISTICS*
* L-Ver only.
DATA RETENTION WAVE FORM
V
4.5V
2.2V
V
CS
GND
FUNCTIONAL DESCRIPTION
* NOTE : X means Don't Care.
CC
DR
liest transition CS going high or WE going high. t
be applied because bus contention can occur.
Data Retention Set-Up Time
CW
AS
WR
V
Data Retention Current
Recovery Time
CC
is measured from the address valid to the beginning of write.
is measured from the later of CS going low to end of write.
is measured from the end of write to the address change. t
CS
H
for Data Retention
L
L
L
Parameter
WE
X
H
H
L
OE
X*
H
L
X
t
SDR
Symbol
WP
t
t
(CS Controlled)
V
I
SDR
RDR
DR
DR
is measured from the beginning of write to the end of write.
Output Disable
CS V
V
V
See Data Retention
Wave form(below)
(T
Not Select
CC
IN
WR
A
Mode
Read
Write
V
= 3.0V, CS V
applied in case a write ends as CS or WE going high.
= 0 to 70 C)
CC
CC
Data Retention Mode
Test Condition
CS V
- 0.2V
- 0.2V or V
- 8 -
CC
- 0.2V
CC
IN
- 0.2V
0.2V
I/O Pin
High-Z
High-Z
D
D
OUT
IN
Min.
2.0
0
5
-
t
RDR
Typ.
-
-
-
-
PRELIMINARY
CMOS SRAM
Supply Current
Max.
0.07
5.5
I
SB
-
-
I
I
I
, I
CC
CC
CC
February-1996
SB1
Unit
Rev 3.0
ms
§Ì
ns
V