CY8C9520A_10 CYPRESS [Cypress Semiconductor], CY8C9520A_10 Datasheet - Page 3

• Manufacturer Part Number: CY8C9520A_10
• Description: 20, 40, and 60 Bit I/O Expander with EEPROM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Architecture
The
block diagram. The main blocks include the control unit, PWMs,
EEPROM, and I/O ports. The control unit executes commands
received from the I
devices and the master device.
The on chip EEPROM can be separated conventionally into two
regions. The first region is designed to store data and is available
for byte wide read/writes through the I
prevent write operations by setting the WD pin to high. All
EEPROM operations can be blocked by configuration register
settings. The second region allows the user to store the port and
PWM default settings using special commands. These defaults
are automatically reloaded and processed after device power on.
The number of I/O lines and PWM sources are listed in the
following table.
Table 1. GPIO Availability
There are four pins on GPort 2 and three on GPort 1 that can be
used as general purpose I/O or EEPROM Write Disable (WD)
and I
settings.
Figure 1
Mode register gives the option to select one of seven available
modes for each pin separately: pulled up/down, open drain
high/low, strong drive fast/slow, or high impedance. By default
these configuration registers store values setting I/O pins to be
pulled up. The Invert register enables inversion of the logic of the
Input registers separately for each pin. The Select PWM register
assigns pins as PWM outputs. All of these configuration registers
are read/writable using corresponding commands in the
multi-port device.
Document Number: 38-12036 Rev. *E
Note
1. This port contains configuration-dependant GPIO lines or A1-A6 and WD lines.
GPort 0
GPort 1
GPort 2
GPort 3
GPort 4
GPort 5
GPort 6
GPort 7
PWMs
Top Level Block Diagram on page 1
Port
2
C-address input (A1-A6), depending on configuration
shows the single port logical structure. The Port Drive
CY8C9520A
5-8 bit
0-4 bit
2
C bus and transfers data between other bus
8 bit
–
–
–
–
–
4
[1]
[1]
CY8C9540A
5-8bit
0-4it
8 bit
8 bit
8 bit
4 bit
–
–
8
2
[1]
[1]
C bus. It is possible to
illustrates the device
CY8C9560A
5-8 bit
0-4 bit
8 bit
8 bit
8 bit
8 bit
8 bit
8 bit
16
[1]
[1]
Figure 1. Logical Structure of the I/O Port
The Port Input and Output registers are separated. When the
Output register is written, the data is sent to the external pins.
When the Input register is read, the external pin logic levels are
captured and transferred. As a result, the read data can be
different from written Output register data. This enables imple-
mentation of a quasi-bidirectional input-output mode, when the
corresponding binary digit is configured as pulled up/down
output.
Each port has an Interrupt Mask register and an Interrupt Status
register. Each high bit in the Interrupt Status register signals that
there has been a change in the corresponding input line since
the last read of that Interrupt Status register. The Interrupt Status
register is cleared after each read. The Interrupt Mask register
enables/disables activation of the INT line when input levels are
changed. Each high in the Interrupt Mask register masks
(disables) an interrupt generated from the corresponding input
line.
Applications
Each GPIO pin can be used to monitor and control various board
level devices, including LEDs and system intrusion detection
devices.
The on board EEPROM can be used to store information such
as error codes or board manufacturing data for read-back by
application software for diagnostic purposes.
Data
PWMs
7 Drive Mode
Pin Direction
Registers
Drive Mode
Drive Mode
Interrupt
Interrupt
Status
Pull-Up
High Z
Mask
CY8C9540A, CY8C9560A
Input Register
Select PWM
Inversion
Register
Output
GPortx
CY8C9520A
Page 3 of 32
8 Bit IO
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